Intel Corporation

Other

Peter L Doyle

Subramaniam M Maiyuran

Abhishek R Appu

Elmoustapha Ould-Ahmed-Vall

Devan Burke

Philip R Laws

Altug Koker

Aditya Sreenivas

Joydeep Ray

Prasoonkumar Surti

Balaji Vembu

Travis T Schluessler

Michael Apodaca

Kamal Sinha

Murali Ramadoss

Thomas A Piazza

Daniel Pohl

Sanjeev S Jahagirdar

Ankur N Shah

Nikos Kaburlasos

Adam T Lake

Kiran Chand Veernapu

John H Feit

Jeffery S Boles

Jacek Kwiatkowski

Hema Chand Nalluri

Eric J Asperheim

Aditya Navale

Pattabhiraman K

Brent E Insko

Val Gene Cook

Saurabh Sharma

Zack Waters

Jason M Surprise

Ingo Wald

James M Holland

Chandrasekaran Sakthivel

Radhakrishnan Venkataraman

Sayan Lahiri

Vivek Tiwari

Daniel D Johnston

Kam Leung

Wing Hang Wong

Tomas G Akenine-Moller

Karthik Vaidyanathan

Abhishek Venkatesh

Arthur Hunter, Jr

Bimal Poddar

Kai Xiao

Kun Tian

Ben J Ashbaugh

Jon N Hasselgren

Carl Jacob Munkberg

Tomer Bar-On

James A Valerio

Hugues Labbe

John G Gierach

David J Cowperthwaite

Robert L Farrell

Wishwesh Anil Gandhi

Kalyan Kumar Bhiravabhatla

Brandon L Fliflet

Nicolas I Kacevas

Joseph Koston

Paul A Johnson

Subramanian Maiyuran

Harri Syrja

Kevin Rogovin

Arthur D Hunter Jr

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Regional adjustment of render rate

One embodiment of a virtual reality apparatus comprises: a graphics processing engine comprising a plurality of graphics processing stages, the graphics processing engine to render a plurality of image frames for left and right displays of a head mounted display (HMD); and foveation control hardware logic to independently control two or more of the plurality of graphics processing stages based on feedback received from an eye tracking module of the HMD, the feedback indicating a foveated region selected based on a current or anticipated direction of a user's gaze, the foveation control hardware logic to cause the two or more of the graphics processing stages to process the foveated region differently than other regions of the image frames.

Apparatus and method for foveated rendering, bin comparison and TBIMR memory-backed storage for virtual reality implementations

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

Position-based rendering apparatus and method for multi-die/GPU graphics processing

A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

Apparatus and method for optimized tile-based rendering

Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.

Dynamic brightness and resolution control in virtual environments

Systems, apparatuses and methods may provide for technology that determines a position associated with one or more polygons in unresolved surface data and select an anti-aliasing sample rate based on a state of the one or more polygons with respect to the position. Additionally, the unresolved surface data may be resolved at the position in accordance with the selected anti-aliasing sample rate, wherein the selected anti-aliasing sample rate varies across a plurality of pixels. The position may be a bounding box, a display screen coordinate, and so forth.

Pre-pass surface analysis to achieve adaptive anti-aliasing modes

Various embodiments enable loop processing in a command processing block of the graphics hardware. Such hardware may include a processor including a command buffer, and a graphics command parser. The graphics command parser to load graphics commands from the command buffer, parse a first graphics command, store a loop count value associated with the first graphics command, parse a second graphics command and store a loop wrap address based on the second graphics command. The graphics command parser may execute a command sequence identified by the second graphics command, parse a third graphics command, the third graphics command identifying an end of the command sequence, set a new loop count value, and iteratively execute the command sequence using the loop wrap address based on the new loop count value.

Method and apparatus for efficient loop processing in a graphics hardware front end

Systems, apparatuses and methods may provide for technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader. More particularly, systems, apparatuses and methods may provide a way to generate, by a write out fixed-function stage, one or more bounding volumes based on geometry data, as inputs to one or more stages of the graphics pipeline. The systems, apparatuses and methods may compute multiple bounding volumes in parallel, and improve the gamer experience, and enable photorealistic renderings at full speed, (e.g., such as human skin and facial expressions) that render three-dimensional (3D) action more realistically.

Write out stage generated bounding volumes

Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch tessellations for the sub-patches. More particularly, systems, apparatuses and methods may provide a way to diverge tessellation sizes to a configurable size within an interior region of a patch or sub-patches based on a position of each of the tessellations. The systems, apparatuses and methods may determine a number of tessellation factors to use based on one or more of a level of granularity of one or more domains of a scene to be digitally rendered, available computing capacity, or power consumption to compute the number of tessellation factors.

Adaptive sub-patches system, apparatus and method

Growing community of inventors

El Dorado, CA, United States of America

Peter L Doyle