International Computers Limited

Peter L Desyllas

Nicholas Peter Holt

John Richard Eaton

Brian J Procter

Barry Gordon Radley

John Austin Jones

Alasdair Rawsthorne

John E Murray

Keith McLaren

George M Bradshaw

Alan Spillar

A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes: USER, HOLD, SHIFT and SELF-TEST modes. These modes are controlled by shifting a control function into a control shift register. When the shifting of the control shift register stops, a command is automatically loaded from the control shift register (or another source) into a command register, which controls the serial shift paths. The provision of a separate command register allows a new control function to be shifted into the control shift register while a preceding command is still active in the command register.

Digital integrated circuits

A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes; USER, HOLD, SHIFT and SELF-TEST modes. Shifting of a path is achieved by putting the path into HOLD mode and then, at each of a series of transfer pulses (TR), putting the path into shift mode for one clock beat. This allows the shifting to be performed at a lower rate than the internal clock rate of the chip; in particular, it can be performed at a rate compatible with a relatively slow diagnostic processor.

Clearance arrangement for data storage apparatus. Data items D are entered into a store 10 together with a tag T equal to the current value of a counter 11. Data items are valid only while the counter 11 retains its current value. When it is desired to clear the store 10 the counter is incremented so that items with the previous tag value are rendered invalid. On some or all of such occasions a fraction of the store locations are also cleared by setting their tags to a null value. By the time the counter has completed a cycle all locations have been cleared in this way and cannot erroneously appear to contain valid data remaining from the previous cycle. The store is out of action to allow it to be cleared only for a relatively short time. Different tag counters may be used for different data types.

Data storage apparatus

Data processing apparatus includes a number of units connected by a bus over which each unit can send public write messages to all the other units in parallel. The units are connected in a loop by means of public write acceptance lines. Whenever a unit receives a public write message it sends an acceptance signal to the next unit in the loop. Each unit produces an error signal if it receives a public write message but does ot receive any corresponding acceptance signal, or if it receives an acceptance signal without having received a corresponding public write message. Thus, each unit checks its neighbors in the loop to ensure correct reception of the messages.

Data processing apparatus with message acceptance monitoring

A data processing system is constructed from processing modules (e.g. LSI chips). Each module contains storage circuits which are connected together, for test and diagnostic purposes, to form a plurality of shift register paths in parallel between common input and output terminals. The common terminals on all the modules are connected to a diagnostic unit by way of common input and output lines. In operation, a first control message from the diagnostic unit is shifted into a master shift register, connected to the common input line, and this causes one of the modules to be selected. A second control message from the diagnostic unit is then shifted into a control shift register in the selected module, and this causes one of the shift register paths in that module to be selected. Test data can then be shifted into the selected path from the diagnostic unit.

Data processing module with serial test data paths

A large-scale integrated circuit chip includes a plurality of bistables connected to combinational logic. In a diagnostic mode, the bistables are operated as a serial shift register, allowing test data to be shifted through the chip between diagnostic input and output pins (LPIN,LPOUT). In a chip test mode, the serial shift register is split into a number of shift register portions, each of which is connected between a separate pair of input and output pins. This allows test data to be shifted through all the shift register portions in parallel so as to speed up testing of the chip.

Testing digital electronic circuits

A data processing system has a two-level storage system in which data items are copied from a main store into a smaller, faster slave store on demand. The mapping of the main store on to the slave store is a many-to-one mapping so that situations will occur where two required data items cannot both be present simultaneously in the slave store because they map on to the same location. The system has special logic which detects this situation and, upon detection, temporarily suspends the use of the slave store and instead uses a smaller first-in first-out area of storage.

Two level store with many-to-one mapping scheme

A hierarchical data storage system comprises a main store and a smaller, faster slave store containing data currently required for processing. The memory system responds to a store access command to retrieve an item of data. In addition, for certain types of store access command, the system performs a look-ahead action to ensure that the slave store is loaded with another data item which forms part of a possible sequence. In certain cases, a test is made to determine whether the possible sequence is in the ascending or descending direction, and the look-ahead access is then made in the appropriate direction.

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Peter L Desyllas