International Business Machines Corporation

Other

Peter L Buchmann

Peter Vettiger

Martin L Schmatz

David J Webb

Otto Voegeli

Kevin Charles Gower

Michael Raymond Trombley

Robert J Reese

Peter Unger

Frank David Ferraiolo

Eric Eugene Retter

Jan Van Lunteren

Thomas Helmut Toifl

Pier Andrea Francese

Ronald Pete Luijten

Christoph S Harder

Andreas Guenther Herkersdorf

Antonius Paulus Engbersen

Michael B Spear

Peter D Hoh

Peter Matthew Thomsen

David Pereira

Volker Graf

Otto Vogeli

Theodor O Mohr

Sylvie Nicot

Bart J Van Zeghbroech

Fran&ccedil;ois G Abel

Clock recovery for a data receiving unit is disclosed. Clock recovery can include obtaining an early/late signal from an incoming data stream. The early/late signal indicates if a set of one or more data samples of the incoming data stream tends to be earlier or later than an edge of a phase-rotated clock signal provided depending on a phase offset value. Clock recovery can include updating a phase rotation counter value in response to the early/late signal. Clock recovery can include determining the phase offset value depending on a rounded phase rotation counter value. The phase offset value can be further determined by selecting one of a set of options including maintaining, increasing, or decreasing the rounded phase rotation counter value. The selecting is performed depending on the early/late signal and depending on the phase rotation counter value.

Clock recovery for a data receiving unit

An interfacing apparatus and related method is provided for configuring to couple a plurality of memory devices being addressable by means of an address space to a processing unit. In one embodiment, the apparatus comprises a first memory access unit being adapted for receiving a memory address from said processing unit and for accessing said memory devices accordingly based on the address provided. It also comprises a second memory access unit being adapted for receiving content data from the processing unit and for controlling a search or update function accordingly for the received content data in one or more of the memory devices. In addition, an allocation unit is also provided for allocating a first part of the address space of the memory devices to said first memory access unit and allocating a second part of the address space of said memory devices to the second memory access unit, each of the memory access units being assigned to corresponding memory devices of the plurality of memory devices.

Apparatus and method for accessing a memory device

A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

Error correcting code protected quasi-static bit communication on a high-speed bus

A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.

Method and apparatus for handling of clock information in serial link ports

A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.

Power-on initialization and test for a cascade interconnect memory system

A method for synchronizing interconnects in a link system according to various embodiments can include receiving input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scrambling the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmitting the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler; synchronizing the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; using an edge detection or transition detection device for synchronization of the descrambler to the scrambler; and de-scrambling the transmitted scrambled data at the receive side resulting in the input data.

Pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling devices and methods

A deskewing circuit configured to receive a main clock signal wherein data bits are misaligned with respect to the main clock signal. A multiphase clock generator coupled to the main clock to generate N/2 clock phases on the rising edge of the main clock and N/2 clock phases on the falling edge. A plurality of n samplers to generate a first set of N/2 sampled signals on the positive phases and a second set of N/2 sampled signals on the negative phases. A corresponding plurality of n phase selectors to determine which phase is the best for each set of sampled signals and generate the two selected signals corresponding to that phase. A control logic block configured to receive a corresponding plurality of n first control signals. A data bus gathering all said selected signals for further processing, wherein said selected signals are aligned with said reference clock but misaligned with respect to each other.

Circuit for bit skew suppression in high speed multichannel data transmission

A real-time load-balancing system for distributing a sequence of incoming data packets emanating from a high speed communication line to a plurality of processing means, each operating at a capacity that is lower than the capacity of the high speed communication line; the system according to the invention comprises: a parser capable of extracting a configurable set of classifier bits from the incoming packets for feeding into a compression means; the compression means is capable of reducing a bit pattern of length K to a bit pattern having a length L which is a fraction of K; a pipeline block for delaying incoming packets until a load balancing decision is found, and an inverse demultiplexer for receiving a port identifier output from said compression means as selector and for directing pipelined packets to the appropriate output port.

Load balancing system, apparatus and method

Cooling structure for direct heat transfer between an active layer of a chip in which electric elements are formed and a heat sink are disclosed. The inventive cooling structure consists of a current/voltage supply level, with metal structures and insulation spacers and/or layers, partly covered by an insulation layer and followed by a heat transfer structure. A heat transfer bridge is in thermal connection with the heat transfer structure that provides for heat flux between the inventive cooling structure and the heat sink. The inventive cooling structure of this invention can be used with semiconductor devices and/or with opto-electronic devices.

Method for making cooling structures for directly cooling an active

Optoelectronic composite consisting of two chips, the first chip 10 being made of a first material, the second one 13 being made of another material. The first chip 10, for example, comprises a multiplicity of active optoelectronic devices e.g. a laser diode 11 and a photo diode 12, all being monolithically integrated. A multiplicity of other optical devices, e.g. a waveguide 16, is monolithically integrated on the second chip 13. In addition this second chip 13 has depressions of the size of the devices 11,12 integrated on said first chip 10. These devices and the waveguide 16 of the second chip 13 are automatically aligned when flipping both chips together.

Bilithic composite for optoelectronic integration

Cooling structures and package modules for semiconductors

A method of passivating etched mirror facets of semiconductor laser diodes which enhances device reliability. The etched mirror facet is first subjected to a weet-etch process to substantially remove any native oxide as well as any surface layer which may have been mechanically damaged during the preceding mirror etch process. Then, a passivation pre-treatment is applied whereby any residual oxygen is removed and a sub-monolayer is formed which permanently reduces the non-radiative recombination of minority carriers at the mirror facet. Finally, the pre-treated mirror surface is coated with a passivation layer to avoid any environmental effect on the mirror.

Method of passivating etched mirror facets of semiconductor laser diodes

A method, and device produced therewith, for improving the planarity of etched mirror facets 18 of integrated optic structures with non-planar stripe waveguides, such as ridge or groove diode lasers or passive devices such as modulators and switches. The curvature of the mirror facet surface at the edges of the waveguide due to topographical, lithographical and etch process effects, causes detrimental phase distortions, and is avoided by widening the waveguide end near the mirror surface thereby shifting the curved facet regions away from the light mode region to surface regions where curvature is not critical.

Growing community of inventors

Langnau am Albis, Switzerland

Peter L Buchmann