Siemens Aktiengesellschaft

Peter Kuecher

Heinrich Koerner

Konrad Hieber

Johann Helneder

Helmuth Treichel

Guenther Roeska

E-Wolfgang Frank

Methods and apparatus for producing conductive layers or structures for VLSI circuits. In a method for producing conductive layers or structures for VLSI circuits, at least two method stages are implemented in direct succession in different chambers of a high-vacuum system without interrupting the high-vacuum conditions for the semiconductor substrate. Avoiding exposure to air between the method stages produces noticeably improved layer properties and enables particularly simple and reliable multi-stage methods for producing conductive layers that promote a multi-layer wiring on the semiconductor substrate. An apparatus for implementing the method has a plurality of high-vacuum process chambers, at least one high-vacuum distributor chamber connecting the process chambers and of at least two high-vacuum supply chambers for semiconductor substrates.

Method and apparatus for producing conductive layers or structures for

A method and apparatus for measuring sheet resistivity of a layer manufactured under the influence of a plasma, wherein a current is generated using two voltage or current sources in a circuit that is composed of a first current branch, a sheet resistivity, and a second current branch. The current includes the parasitic current I.sub.P injected into the layer by the plasma, this having a first and second part which are symmetrically supplied into the two current branches which respectively have an identical resistance overall. The currents I.sub.A and I.sub.B thus actually flowing in the first and second current branch are respectively directly measured, or measured on the basis of the voltage drop-off at known precision resistors. A measured current I.sub.M which is independent of the plasma influence is calculated therefrom by averaging, and the sheet resistivity is calculated from I.sub.M and by measuring the voltage drop-off at the sheet resistivity.

Method for the in situ identification of the sheet resistivity or,

An improved planarization and reliability for low-impendance interconnects in multi-layer wiring of integrated semi-conductor circuits is provided. The circuit comprises at least two metallization levels composed of aluminum or of an aluminum contact, tungsten is employed as a via hole filler and metal silicides are employed as intermediate layers. The metallization pattern contains a nucleation layer preferably composed of titanium/titanium nitride as an under-layer for every metallization level, whereby the electron migration resistance of the aluminum layers is enhanced and a layer preferably composed of molybdenum silicide is used as a cover layer for every metallization level, thereby improving the low-impedance of the metallization. The sandwich-like metallization structure improves the planarity and the thermal stability of the circuit. Since the number of metallization levels is arbitrary, the present invention can be used for VLSI circuits.

Integrated semi-conductor circuit comprising at least two metallization

To improve the planarization and reliability of low-impedance aluminum metallizations, a substrate provided with a titanium/titanium nitride double layer diffusion barrier layer and having a contact hole is provided or, respectively, filled with an aluminum/silicon alloy sandwich structure composed of a sequence of n aluminum/silicon layers having n-1 intermediate layers of titanium applied thereon, whereby the layer thickness ratio of the titanium intermediate layers to the overall layer thickness d of the metallization behaves like 1:10. The multisandwich metallization manufactured in this way is used in VLSI circuits and, given the same specific resistance achieves a life expectancy that is 10 through 100 times higher than that of the aluminum/silicon/titanium alloys that are otherwise standard.

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Wuppertal, Germany

Peter Kuecher