Lsi Logic Corporation

Peter Korger

Robert Wayne Moss

Brian Francis Schoner

Christopher M Giles

David O Sluiter

Mark Jon Kwong

An apparatus including a plurality of first base circuits, a plurality of second base circuits, a first test circuit, a second test circuit, and a test path. The plurality of first base circuits may be coupled to the plurality of second base circuits via one or more base circuit paths on a layout. The first test circuit may be disposed in a first distal location of the layout. The second test circuit may be disposed in a second distal location of the layout. The test path may be configured to (i) couple the first test circuit to the second test circuit and (ii) generate a test time delay from the first test circuit to the second test circuit incrementally longer than a maximum time delay generated by any of the base circuit paths.

Long path at-speed testing

A circuit comprising a register stack and a control circuit. The register stack may be configured as (i) a plurality of segments addressable through a segment address signal and (ii) a plurality of registers within each of the plurality of segments. The plurality of registers are generally addressable through a register address signal. The control circuit may be configured to (i) store a plurality of register states, (ii) store a segment count signal, and (iii) present the segment address signal responsive to the plurality of register states, the segment count signal, and the register address signal.

Configurable hardware register stack for CPU architectures

An input/output characterization register is provided for characterizing an integrated circuit input or output. The register includes a normal data input, a characterization data input, and a data latch having a latch control input, a latch data input and a latch data output. The normal data input and the characterization data input are multiplexed with the latch data output to the latch data input.

Input/output characterization chain for an integrated circuit

An apparatus including a first circuit and a second circuit. The first circuit may be configured to present a first data signal and a first indicator signal in response to a first clock signal and an enable signal. The second circuit may be configured to present a second data signal and a second indicator signal in response to the first data signal, the first indicator signal and a second clock signal.

Data ready indicator between different clock domains

A memory controller for aligning write data and a clock strobe signal provided to a memory device includes a delay line coupled to a local clock input and providing as an output a delayed local clock signal. A first latch circuit receives data to be written to the memory device as an input and has an output coupled to a data input of the memory device. The first latch circuit is clocked by a first one of the local clock signal and the delayed local clock signal and provides in response the write data to the data input of the memory device. A clock strobe generating circuit is clocked by a second one of the local clock signal and the delayed local clock signal. The clock strobe generating circuit has an output coupled to a clock strobe input of the memory device and provides the clock strobe signal to the memory device.

Memory controller and method of aligning write data to a memory device

A system and method are presented for indicating active tag bits within valid entries of a dual-clock FIFO data buffer, used to transfer data between two clock domains. Data (containing tag bits) are written to the FIFO and read from the FIFO using separate clocks. Data writes are synchronous with the first clock, while reads are synchronous with the second clock. A FIFO entry is 'valid' after data has been written to it, and before it is read. The system disclosed herein identifies the valid FIFO entries and generates a set of logic outputs, synchronized to the second clock (i.e., the read clock). Each output corresponds to one of the tag bit positions, and is HIGH if the corresponding tag bit is HIGH in any of the valid entries. This creates a means of detecting active tag bits in the FIFO without having to actually read each entry. Since the tag bits convey important information about the source and nature of the data, this detection system may expedite the data transfer. A simple implementation of the method is described, based primarily on conventional combinatorial logic. The method is straightforward and can readily be incorporated into an integrated circuit.

Storage device, system and method which can use tag bits to synchronize queuing between two clock domains, and detect valid entries within the storage device

A method and apparatus are provided for testing linearity of two or more programmable delay chains in an integrated circuit. A first delay chain is successively programmed to a first sequence of delay settings and, for each delay setting in the first sequence, a second delay chain is successively programmed to a second sequence of delay settings. The second sequence sweeps a propagation delay through the second delay chain from a delay value less than a present propagation delay through the first delay chain to a delay value greater than the present propagation delay. For each delay setting of the second delay chain, a logic transition is applied to inputs of the first and second delay chains and the output of one of the first and second delay chains is latched as a function of the output of the other of the first and second delay chains to produce a sample value. The sample values produced for each delay setting in the first sequence are monitored to determining whether the logic transition occurs in the sample values within an expected time window.

Physical linearity test for integrated circuit delay lines

Methods and associated structure for realignment of returned read data from the memory component to the memory controller to adjust for phase shift in the memory device's supplied strobe signals due to propagation delays and other layout, fabrication and environmental factors. The realignment features of the present invention impose a calibrated delay on the memory controller's clock signal used to sample registered read data from the memory components. By so adjusting the alignment of returned read data with respect to the memory controller's clock, the present invention obviates the need for an asynchronous FIFO as is presently commonly practiced in the art to avoid such phase shifts between memory components and associated memory controller's.

Methods and structure for read data synchronization with minimal latency

A method an apparatus are provided for calibrating a mask signal which is used for masking a data strobe signal that is received from a memory device with read data. According to the method, one or more read operations are performed with the memory device, and the data strobe signal is sampled at a plurality of different time delays relative to a local clock signal to produce a plurality of data strobe sample values. The plurality of data strobe sample values are searched to identify a temporal location within a preamble phase of the data strobe sample values and one of the time delays that corresponds to the temporal location. A delay at which the mask signal is disabled in response to a read operation is then set relative to the local clock signal based on the time delay corresponding to the temporal location.

Method and apparatus for calibrating DQS qualification in a memory controller

A method and apparatus are provided for capturing data read from a memory device that is aligned with respect to a clock strobe signal originating from the memory device, which has constraints with respect to a local clock signal supplied to the memory device. The apparatus includes a circuit for capturing the data read from the memory device relative to the clock strobe signal to produce captured read data, a circuit for latching the captured read data relative to a sample clock signal, and a circuit for measuring a phase difference between the sample clock signal and the clock strobe signal and adjusting a phase of the sample clock signal as a function of the phase difference.

Method and apparatus for measuring the phase of captured read data

A phase measurement circuit includes first and second complementary clock strobe inputs, a local clock input and a sample clock output. A programmable delay line is coupled between the local clock input and the sample clock output and has a plurality of propagation delay settings. First and second toggle circuits are clocked by the first and second clock strobe inputs, respectively, and each has a toggle output that changes state when clocked by the respective first or second clock strobe input. A capture latch circuit has first and second data inputs coupled to the toggle outputs of the first and second toggle circuits, respectively, has first and second capture outputs, and is clocked by the sample clock output. A synchronizer circuit has first and second data inputs coupled to the first and second capture outputs, respectively, has first and second synchronized capture outputs, and is clocked by the local clock input.

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Frederick, CO, United States of America

Peter Korger