Ams Ag

Peter Kammerlander

Thomas Jessenig

Christian Halper

Gerhard Loipold

A charger control circuit (CC) comprises a first charger terminal (CT) and a system terminal (ST) and is configured to assign a voltage applied at the first charger terminal (CT) to one of at least three voltage ranges by performing at least one voltage comparison. The charger control circuit (CC) is configured to determine and distinguish, based on the assignment, whether an external charger (EXC) or a secondary battery (SBAT) is connected to the first charger terminal (CT). Furthermore, the charger control circuit (CC) is configured to, depending on a predetermined operating state of the first charger terminal (CT), supply power from the secondary battery (SBAT) or the external charger (EXC) to a portable electronic device via the system terminal (ST) when the secondary battery (SBAT) or the external charger, respectively, is connected to the first charger terminal (CT).

Charger control circuit and method for charger control

A converter arrangement, in particular a switched DC/DC converter arrangement, comprises a control die and a converter die. The control die comprises a control logic for generating a control signal and a control output for controlling the converter die by means of the control signal. The converter die comprises at least one converter that is designed for converting an input signal into an output signal in dependence on the control signal, wherein the control signal can be received at a control input. A single-line interface connects the control output to the control input.

Converter arrangement having a control die with control logic for generating a control signal and a control output for controlling a converter die

Bidirectional temperature communication between controller and converter for multiple phase buck converters

The invention relates to a circuit and to a method for generating a start sequence. The circuit comprises at least one partially programmable memory (nonvol) for storing an encoded start sequence (Ni) and a control unit (CTRL), which is equipped to read the encoded start sequence (Ni) and decode it into a decoded start sequence (dNi) and to generate a target register address (n) depending on the decoded start sequence (dNi). An addressable memory (vol) is provided, to which the decoded start sequence (dNi) can be written by means of the control unit (CTRL) at the target register address (n).

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Graz, Austria

Peter Kammerlander