Intel Corporation

Peter K Moon

Valery M Dubin

Makarem A Hussein

Kevin Fischer

Jun He

Ying Zhou

Ebrahim Andideh

Grant M Kloster

Chris E Barns

David H Gracias

Jihperng Leu

Daniel C Diana

Lee D Rockford

David T Krick

Kevin O'Brien

Reza Arghavani

Michael L McSwiney

Steven W Johnston

Madhav Datta

Zhiyong Ma

Payman Aminzadeh

Kerry L Spurgin

Mark T Bohr

Alan M Myers

Michael D Goodner

Robert P Meagley

Sarah E Kim

R Scott List

Chin-Chang Cheng

Sam Sivakumar

Kevin P O'brien

Anna M George, Legal Representative

Lawrence N Brigham

Seiichi Morimoto

Berni W Landau

Angelo Kandas

Charles H Recchia

Bob Martell

Dave Ayers

Jim Powers

Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.

Interconnects having sealing structures to enable selective metal capping layers

Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.

Forming a copper diffusion barrier

In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.

Method for an improved air gap interconnect structure

Apparatus for an improved air gap interconnect structure

The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. The present invention further includes a structure having a substrate, the substrate having a device; an insulator disposed over the substrate, the insulator having an opening, the opening disposed over the device; a barrier layer disposed over the opening; a seed layer disposed over the barrier layer; and a protection layer disposed over the seed layer.

Protection of seedlayer for electroplating

Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.

Methods and apparatuses for producing a polymer memory device

Method and apparatus for an improved air gap interconnect structure

An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.

Selectively converted inter-layer dielectric

A method of depositing a metal cladding on conductors in a damascene process is described. The potential between, for instance, cobalt ions in electroless solution and the surface of an ILD between the conductors is adjusted so as to repel the metal from the ILD.

Method for improving selectivity of electroless metal deposition

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Portland, OR, United States of America

Peter K Moon