Intel Corporation

Peter K Hazen

Charles W Brown

Sanjay S Talreja

Robert E Larsen

Rodney R Rozman

Sandeep K Guliani

Sherif R Sweha

Robert N Hasbun

Jerry A Kreifels

Terry L Kendall

Michael J Castillo

Vishram P Dalvi

Christopher John Haid

Ranjeet Alexis

Alan E Baker

David A Leak

Thomas C Price

Collin Ong

Fasil G Bekele

Mark E Bauer

Duane R Mills

Sachidanandan Sambandan

Deborah L See

Kevin W Frary

Terry D West

Michael P Vital

A method and apparatus for preempting an operation in a nonvolatile writeable memory is performed using a pin. Preempting an operation is accomplished by either suspending the operation or by aborting the operation. Once an operation is suspended in the nonvolatile writeable memory, other operations can then be performed. Subsequently the suspended operation may be resumed.

Nonvolatile writeable memory with preemption pin

A processor-implemented method is described for updating a datum stored in a nonvolatile memory, bits of which cannot be overwritten from a first logical state to a second logical state without a prior erasure. A first storage location in the memory that stores a first version of the datum is accessed. A status field of the first storage location is checked to determine whether the first version of the datum has been superseded. If the status field of the first storage location indicates that the first version of the datum has not been superseded, then a most recent version of the datum is stored in a second storage location of the memory. An address of the second storage location is then written into a next location address field of the first storage location and the status field of the first storage location is written to indicate that the first version of the datum has been superseded such that the datum is updated without the prior erasure of the memory. If the status field of the first storage location indicates that the first version of the datum has been superseded, then the next location address field of the first storage location is accessed to obtain the address of a next storage location that stores a second version of the datum that supersedes the first version of the datum. The next storage location is then caused to be the first storage location and the method repeats itself to access the first storage location. An apparatus for storing a datum is also described.

Electrically erasable and programmable memory that allows data update without prior erasure of the memory

A method and apparatus for controlling use of an electronic system is described. Use of the electronic system is controlled by programming at least one unique code into an auxiliary memory of the electronic system. The auxiliary memory is a permanently lockable memory that is located outside of a main memory array space. The unique code is compared to at least one component code. Use of the electronic system is controlled based on a predefined relationship between the unique code and the component code.

Method and apparatus for preventing the fraudulent use of a cellular telephone

An interface for a read-while-write memory. A memory device includes a single-chip memory array and an interface that is responsive to one or more commands to configure the memory array in a read-while-write configuration.

Method and apparatus for placing a memory in a read-while-write mode

An apparatus for protecting memory blocks in a block-based flash Erasable Programmable Read Only Memory (EPROM) device is disclosed. A non-volatile memory array includes a number of blocks that are capable of being placed in a locked state or an unlocked state. A volatile lock register and transmits a write protect signal and a volatile lock-down register are coupled to a lockable block in the volatile memory array. A hardware override line is coupled to both the lock register and the lock-down register. The hardware override line temporarily overrides operation of the lock-down register when it transmits a signal at a first logic state. The lock down register may be used to prevent programming of an associated lock register. The lock registers and lock down registers may be embodied in static access memory (SRAM) circuits. A command buffer may be operable to transmit a two cycle command including a first command specifying whether a lock configuration is to be changed and a second command specifying whether a block is to be placed in a lock state, an unlock state, or locked down state. The lock down registers may be capable of being set to lock down only once during a period in which the apparatus is powered up.

Apparatus and method using volatile lock and lock-down registers and for

A programmable logic device that includes a voltage input and a detection circuit coupled to the voltage input is described. The detection circuit detects whether a voltage applied to the voltage input exceeds a predetermined value. The programmable logic device also includes a configuration circuit coupled to the detection circuit. The configuration circuit configures the programmable logic device to receive a current sufficient for program and erase operations through the voltage input in response to the detection circuit detecting that the voltage exceeds the predetermined value.

Method and apparatus for fast production programming and low-voltage

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Nonvolatile writeable memory with program suspend command

A method and apparatus for partitioning a flash memory device is provided. The flash memory device includes a plurality of partitions, each partition able to be read, written, or erased simultaneously with the other partitions.

Flash memory partitioning for read-while-write operation

A method and apparatus suspend operations in a flash memory in order to read code from the flash memory. A system comprises a processor and a nonvolatile writeable memory coupled together. A non-read operation is preempted in the nonvolatile writeable memory responsive to an input at a pin of the nonvolatile writeable memory. The preemption occurs by either suspending the non-read operation or aborting the non-read operation. Code is read from the nonvolatile writeable memory and provided to the processor. Subsequently, the non-read operation is resumed at where it was suspended, or is started anew.

Method and apparatus for preempting operations in a nonvolatile memory

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

Method and apparatus for suspending the writing of a nonvolatile

A method and apparatus for protecting data stored in a nonvolatile memory. First, a system to which an interface is coupled asserts a first signal that is one of two voltages. In addition, the system to which the interface is coupled asserts a second signal that is one of two voltages. The interface comprises circuitry that translates these two signals into a third signal that is one of three voltages. This third signal is then passed to and used by the nonvolatile memory to place the memory into one of three different protection modes.

Method and apparatus for controlling the protection mode of flash memory

A nonvolatile memory includes a memory array and a control circuit having a command latch and a command decoder. The control circuit receives an output enable signal and a write enable signal to control memory operations of the memory array in accordance with a command latched into the command latch via the command decoder. A write protection circuit is also provided that disables the command latch and the command decoder when the output and write enable signals are both active. The protection circuit includes a pulse generator that generates a reset signal to reset the command latch to the read array state and a control logic that causes the pulse generator to assert the reset signal when an output enable signal and a write enable signal of the memory are both active until after the write enable signal has been forced internally inactive and the command latch closed.

Nonvolatile memory with a write protection circuit

A method and apparatus for protecting data stored in a nonvolatile memory. First, a locking signal is initiated to indicate to the memory that write and erase operations are to be prevented. Next, in response to this locking signal, the supply voltage that supports write and erase operations in the memory is lowered below a threshold value. In doing so, protection circuitry that is contained within the memory prevents write and erase operations in the memory.

Method and apparatus for protecting data stored in flash memory

A nonvolatile memory includes a memory array, control circuitry coupled to the memory array for controlling memory operations with respect to the memory array, and a configuration cell coupled to the control circuitry for generating a configuration signal to configure the nonvolatile memory with respect to the memory operations. The configuration cell can be programmed in a first state and a second state. A configuration logic is coupled to the configuration cell and the control circuitry for altering the configuration signal from the configuration cell to the control circuitry without causing the configuration cell to be reprogrammed. The configuration logic includes an exclusive or gate that temporarily alters the configuration signal without affecting a programmed state of the configuration cell. The configuration logic can also disable the configuration signal to the control circuitry and configure the nonvolatile memory with a temporary configuration information stored in a configuration register of the configuration logic.

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Auburn, CA, United States of America

Peter K Hazen