Adaptec, Inc.

Peter K Cheung

Christopher R Burns

Barry Allen Davis

Kin C Doe

James R Lindeman

Anton B Rang

Tonghan Tee

Daniel Olin Skeen

Abdul Waheed Mohammed

Gordon A Minami

Disclosed is a SCSI host adapter for use in a computer system. The SCSI host adapter is configured to provide the computer system with interconnection with internal and/or external target devices. The SCSI host adapter includes a low voltage differential connector for interconnecting to a low voltage differential bus, and the low voltage differential bus is configured to communicate a first transaction. The SCSI host adapter also includes a single ended connector for interconnecting to a single ended bus, and the single ended bus is configured to communicate a second transaction. Furthermore, the SCSI host adapter includes a transceiver unit that is configured to interface between the low voltage differential bus and the single ended bus and produce a target information signal. The target information signal is configured to indicate whether the first transaction or the second transaction is occurring between the SCSI host adapter and the low voltage differential bus or the single ended bus.

SCSI bus transceiver and method for making the same

When more than two terminators are on a SCSI bus the bus is said to be 'over-terminated', and when less than two terminators are on the bus, the bus is said to be 'under-terminated'. When the SCSI bus is either under or over terminated, the bus does not function, and often the user does not know why the bus is not functioning. Apparatus and a method are provided for indicating to the user when the bus is not properly terminated. A terminator monitoring system and method operate in conjunction with the bus. A precision resistor is connectable to the bus so that a voltage drop is produced across the precision resistor. A circuit monitors the value of the produced voltage drop across the precision resistor to provide an indication of the number of terminators on the bus. A switch selectably connects the precision resistor to the bus, and there is a source of a reference voltage. The monitoring circuit includes a comparison circuit responsive to the voltage drop across the precision resistor and to the reference voltage for indicating whether the number of terminators on the bus exceeds a limit or is less than the limit. The system notifies a system user of an undesired (or improper) termination condition of the bus, wherein each of a plurality of devices connected to the bus may have a termination enabled.

Methods of and apparatus for monitoring the termination status of a SCSI

Disclosed is a host adapter having automatic termination, and a method for implementing the automatic termination. The host adapter includes a first connector for connecting to at least one external peripheral device and a second connector for connecting to at least one internal peripheral device. The host adapter further includes a termination system circuit that is coupled between the first connector and the second connector. The termination system circuit is configured to produce bit data that is indicative of whether a peripheral device is coupled to one or both of the first connector and the second connector. Preferably, the termination system circuit communicates the bit data to a software termination engine upon boot-up to enable or disable a termination of the host adapter. Furthermore, the termination system circuit includes a termination control decoder and a tri-state buffer. The host adapter also includes a termination over-ride control that is configured to over-ride the automatic termination generated by the termination system circuit via a software control.

Bus termination circuitry and methods for implementing the same

A PCI to SCSI host adapter circuit is provided for use with different types of host platforms. The host adapter includes logic and controller circuits, and a memory having multiple drivers and a bank switching instruction set stored therein. During initialization, the first driver is loaded into the host's memory if the host's processor is of a compatible type. Otherwise, the bank switching instruction set is loaded into the host's memory and interpreted by the host's processor. During interpretation, the bank switching instruction set causes the host's processor to signal the logic circuit to request that the controller circuit re-map another driver to the location of the first driver in the memory. After this bank switching has occurred, the selected driver is loaded into the host's memory, provided of course that the host's processor is of a compatible type. This process may be repeated until the appropriate code type is found or the host processor is not supported.

Growing community of inventors

Milpitas, CA, United States of America

Peter K Cheung