Intel Corporation

Peter K Charvat

Thomas A Letson

Alan M Myers

Shi-Ning Yang

Peng Bai

Robert S Chau

Gilroy J Vandentop

Chi-Hwa Tsang

Melton C Bost

Krishnamurthy Murali

Robert C Lindstedt

Kevin F Carmody

Patricia Stokley

Ralph Schweinfurth

Robert M Guptill

Maxine Fassberg

Lynn A Price

Chris Kardas

A structure is provided comprising a semiconductor substrate, a gate oxide layer on the substrate, and a polysilicon layer on the gate oxide layer. A masking layer is formed on the polysilicon layer. The masking layer is then patterned into a mask utilizing conventional photolithographic techniques, but without patterning the polysilicon layer. The photoresist layer is then removed, whereafter the mask, which is patterned out of the masking layer, is utilized for patterning the polysilicon layer. The use of a carbon free mask for patterning the polysilicon layer, instead of a conventional photoresist layer containing carbon, results in less breakthrough through the gate oxide layer when the polysilicon layer is patterned. Less breakthrough through the gate oxide layer allows for the use of thinner gate oxide layers, and finally fabricated transistors having lower threshold voltages.

Method of patterning a layer for a gate electrode of a MOS transistor

A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

Via hole profile and method of fabrication

Anchored via connection

The present invention discloses a method for the etching of insulating films, specifically silicon oxide films, using a fluorine-helium-oxygen gas mixture in the fabrication of semiconductor devices. The method utilizes a prior art reactive ion etch system and adds a quantity of helium to a pre-established fluorine-oxygen chemistry to reactively etch the silicon oxide film while minimizing the occurrence of gate charging resulting from damage to the gate oxide. The addition of helium gas into the etch chemistry must be such that the flow of helium is at least 20% of the sum of the total fluorine, helium, and oxygen flows. The resulting etch chemistry, which can be used in any commercially available reactive ion etch system, produces a more uniform etch while reducing gate oxide damage so as to minimize charging of the semiconductor gate.

Method for etching silicon oxide films in a reactive ion etch system to

A dry process for stripping photoresist from a polyimide surface formed on a substrate is described. The present invention is practiced after a polyimide layer has been etched. Prior to etching, the polyimide surface is masked with photoresist which is then patterned. The polyimide is etched in exposed regions, for example to form vias to expose contacts located beneath the polyimide layer. The present invention then strips the photoresist in a single wafer downstream plasma etcher in a plasma comprising oxygen radicals. The polyimide is subjected to a short preheat before introduction of the oxygen plasma, and is also heated during the stripping process. The strip proceeds until an endpoint is detected. The endpoint is detected by a change in the spectral emission of the plasma which occurs due to a decrease in the amount of CH.sub.3 radicals present in the system when the polyimide surface is reached. A short timed over-etch is then employed to ensure complete removal of the photoresist. The stripping process of the present invention selectively strips photoresist compared to polyimide, so that exposed portions of the polyimide surface are not significantly etched during the timed overetch.

Dry process for stripping photoresist from a polyimide surface

A process for forming a protective polyimide layer over a semiconductor substrate includes the steps of curing a deposited polyamic acid layer at a temperature which is sufficient to reduce the etch rate of the acid layer when subsequently exposed to a developer. After formation of a photoresist masking layer over the polyamic acid, the substrate is exposed to a developer to define a plurality of bonding pad openings therein. The developer permeates into the acid layer to form a salt in the regions beneath the openings. Subsequent hardbaking imidizes the polyamic acid, but not the salt regions. Removing the photoresist layer also develops the polyimide which removes the salt regions to expose the underlying bonding pads.

Polyimide process for protecting integrated circuits

An anisotropic reactive ion etching of an aluminum metal film of a semiconductor device. The device is placed in a reactive ion etcher using a CF.sub.4, Cl.sub.2 and BCl.sub.3 gas mixture to anisotropically etch the aluminum metal film layer wherein the gas mixture has a ratio of CF.sub.4 :Cl.sub.2 such that the aluminum etch rate increases as the amount of CF.sub.4 relative to Cl.sub.2 increases.

High CF.sub.4 flow-reactive ion etch for aluminum patterning

Growing community of inventors

Portland, OR, United States of America

Peter K Charvat