International Business Machines Corporation

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Peter Juergen Klim

Christopher McCall Durham

Jose Angel Paredes

Sam Gat-Shang Chu

Michael Ju Hyeok Lee

Chung H Lam

Viktors Berstis

Owen Chiang

James Douglas Warnock

Satyajit Dutta

Zhibin Cheng

Matthew J Amatangelo

William Elton Burky

John Beck

Jethro C Law

Trong V Luong

Roy Keith Waite

Hung Qui Le

Kerry Bernstein

Paul Joseph Jordan

Paul David Kartschoke

Donald Lawrence Wheater

Michael J Lee

Taqi Nasser Buti

Sam G Chu

Srinivas Patil

Ronald Gene Walther

Jerome L Cann

James Edward Dunning

Robert N Krentler

Rafik F Dagher

Tak H Ning

David William Boerstler

Hung Cai Ngo

Stanley Everett Schuster

Albert James Van Norstrand, Jr

Marlin Wayne Frederick, Jr

Daniel Lawrence Stasiak

Lloyd Andre Walls

Donald George Mikan, Jr

Michael Kevin Ciraula

Byron Lee Krauter

Dennis L Moeller

Nandor G Thoma

Stephen Larry Runyon

Robert Greg McDonald

Abraham Mathews

Hieu T Ngo

Mark G Noll

Jose A Olive

Grant L Clarke, Jr

Willem Bernard Van Der Hoeven

Robert N L Krentler

Younes Lofti

Shon Alan Schmidt

Abraham Matthews

Avery M Lyford

Jennifer Michelle Bernard

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. C4 bonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a C4 carrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

Test structure and methodology for three-dimensional semiconductor structures

A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. Cbonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a Ccarrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.

A design structure for noise suppression. A design structure has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.

Structure for reduced area active above-ground and below-supply noise suppression circuits

A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.

Structure for automated transistor tuning in an integrated circuit design

A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.

Memory device with control circuit for regulating power supply voltage

A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical '1'), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.

Structure for a configurable low power high fan-in multiplexer

Embodiments that decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one or more elements to conserve power after an input signal remains unchanged for a period of time. Another embodiment reduces power consumption in a circuit, the embodiment comprising a swing module coupled with a swing selector and an output controller. The swing module may generate full or low swing signals depending on the state of the swing selector. The output controller may increase the output impedance of the swing module after an input signal to the swing module remains unchanged for a quantity of time. Various apparatus embodiments include portable computing devices and cellular telephones.

High-speed low-power integrated circuit interconnects

A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.

Transmission gate multiplexer

A technique for clock gating a clock domain of an integrated circuit includes storing first, second, and third values in a control register. The first value corresponds to a first number of clock cycles to wait before initiating clock gating, the second value corresponds to a second number of clock cycles in which clock gating is performed, and the third value corresponds to a third number of clock cycles in which clock gating is not performed. One of the first, second, and third values is selectively loaded from the control register into a counting circuit. The counting circuit counts from the loaded one of the first, second, and third values to a transition value. A compare signal is received at the control state machine (from the counting circuit) that indicates the counting circuit has reached the transition value. Based on a current state of the control state machine, a load signal is provided to the counting circuit to cause the counting circuit to load an associated one of the first, second, and third values from the control register.

Techniques for reducing power requirements of an integrated circuit

A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.

High performance, low power, dynamically latched up/down counter

A system and method of selective row energization based on write data, with a selective row energization system including a storage arrayhaving M rowsand N columns; an N-bit data word register; a uniform-detect circuitresponsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect registerhaving M uniform-detect latches, each being associated with one of the M rowsand storing the uniform word data bit for the data word stored in the associated M row; and an M-bit row driver deviceresponsive to the uniform word data bit for each of the M rowsto inhibit energization of the M rowsfor which the uniform word data bit is the first value.

System and method of selective row energization based on write data

A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

Limited switch dynamic logic cell based register

Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to 'head' and 'foot', or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain &#x201c;virtual&#x201d; voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.

Virtual power rails for integrated circuits

A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.

Reduced area active above-ground and below-supply noise suppression circuits

A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.

Transient noise detection scheme and apparatus

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Austin, TX, United States of America

Peter Juergen Klim