Intersil Americas Inc.

Nortel Networks Corporation

Elantec Semiconductor, Inc.

Renesas Electronics America Inc.

Peter John Mole

Philip Golden

Philip V Golden

Wei P Chen

Barry Harvey

Xin Zhang

Gwilym Francis Luff

Barry Concklin

Daryl Chamberlin

Jayant Vivrekar

Dimitrios Katsis

Morgan Tang

Gregory Weng Yuen

Chettan Babla

Henric Van Vliet

One or more embodiments enable both a fixed bandgap reference voltage and a variable reference voltage to be generated and stored on a capacitor. According to certain aspects, the present embodiments use an additional storage capacitor of smaller size to reduce the sub-threshold leakage of an isolating FET switches at high temperatures. Among other aspects, this enables a more efficient use of chip area for reducing sub-threshold induced leakage than simply increasing the storage capacitor when precision storage is required.

Low leakage CMOS switch to isolate a capacitor storing an accurate reference

A remote differential voltage sensing circuit having a voltage input (Vin) and a voltage output (Vout), comprises a dual differential input stage including a common-source or common-collector differential input stage in parallel with a common-gate or common-base differential input stage. The common-source or collector differential input stage has differential inputs, one coupled to the voltage input (Vin) and the other coupled to the voltage output (Vout). The common-gate or common-base differential input stage has differential inputs, one coupled to a local ground (Agnd) and the other coupled to a remote ground (Rgnd). An output stage is driven by an output of the dual differential input stage and produces an output voltage at the voltage output (Vout). A compensation network is coupled between the voltage output (Vout) and the output of the dual differential input stage.

Remote differential voltage sensing

Methods, systems and devices described herein improve vertical resolution at sides of a four cornered image produced by a scanning projector display device. In accordance with an embodiment, a first plurality of frames (e.g., odd frames) of the image are scanned back and forth from side to side starting at a first line level, in one of the corners. Additionally, a second plurality of frames (e.g., even frames) of the image are scanned back and forth from side to side, starting at a vertical offset level from the first line level, in the same one of the corners. The scanning of the first plurality of frames (e.g., the odd frames) is interleaved with the scanning of the second plurality of frames (e.g., the even frames).

Systems and methods to improve spatial resolution on back and forth scanning display devices

Embodiments of the present invention relate to methods and circuits for use with a system including a light emitting element (e.g., a laser diode or light emitting diode) that is driven by a current produced by a current output digital-to-analog converter (DAC), wherein the light emitting element or the DAC is powered by a supply voltage produced by a voltage supply. In accordance with an embodiment, a measure indicative of a voltage at an output of the DAC is obtained, wherein the voltage at the output of the DAC is indicative of a voltage headroom available for the DAC. The measure indicative of the voltage at the output of the DAC is compared to one or more predetermined references, and the supply voltage is controlled based on the comparison(s).

Systems and methods for dynamic power management for use with a video display device

Provided herein are methods and circuits that reduce a differential capacitance at differential nodes of a differential circuit while boosting the common mode capacitance at the differential nodes, where the differential circuit includes a pair of inputs and differential outputs. A negative capacitance is generated between differential nodes of the differential circuit, which can be accomplished by connecting a negative capacitance circuit between the differential nodes of the differential circuit. In an embodiment, the negative capacitance circuit is connected in parallel with the differential outputs of the differential circuit. In another embodiment, the negative capacitance circuit is connected in parallel with the inputs of the differential circuit. In still another embodiment, the negative capacitance circuit is connected in parallel with the differential internal nodes (i.e., nodes other than the input and output nodes) of the differential circuit.

Negative capacitance synthesis for use with differential circuits

Provided herein are amplifiers including negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of output stages of such amplifiers. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion. Also provided herein are methods for use with amplifiers including an output stage, including connecting a negative capacitance circuit in parallel with a base-emitter capacitance of the output stage.

Amplifiers with negative capacitance circuits

Provided herein are negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of an output stage. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion.

Negative capacitance synthesis

An embodiment of an amplifier includes an amplifier output node operable to provide an output signal, and an output stage. The output stage includes a drive buffer having an input node and an output node, a drive transistor, and a compensation capacitor. The drive transistor has a control node coupled to the output node of the drive buffer, a first drive node, and a second drive node coupled to the amplifier output node. And the compensation capacitor has a first node isolated from the control node of the drive transistor by the drive buffer, and has a second node coupled to the amplifier output node. By buffering the control node of the drive transistor, one may reduce the level of nonlinear current referred back to the amplifier input as a nonlinear offset voltage, and thus may reduce the level of nonlinear distortion that his nonlinear offset voltage generates at the amplifier output.

Amplifier with improved compensation topology and related amplifier circuit, system, and method

Methods and circuits for extracting a true mean of two signals are provided. A first amplifier input stage (e.g., an n-type stage) is operated when a mean of the two signals approaches an upper rail voltage. A second amplifier input stage (e.g., a p-type stage) is operated when the mean of the two signals approaches a lower rail voltage. A transitioning circuit controls how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage, when the mean of the two signal does not approach either of the rail voltages. An output of the high-gain amplifier output stage is fed back to both the first and second amplifier input stages via a feedback stage, which can be a matched buffer stage.

Methods for extracting the mean (common mode) voltage of two input signals

A rail-to-rail operational amplifier to extract a true mean of two signals. The amplifier includes a first amplifier input stage adapted to operate when a mean of the two signals is near an upper rail voltage. A second amplifier input stage is adapted to operate when the mean of the two signals is near a lower rail voltage. A transitioning circuit is adapted to control how much each of the first and the second amplifier input stages contributes to an input of a high-gain amplifier output stage. An output of the high-gain amplifier output stage is fed back to both the n-type amplifier input stage and the p-type amplifier input stage via a matched buffer stage.

Rail-to-rail operational amplifier circuits to extract the mean (common mode) voltage of two input signals

To reduce the impact of image frequencies generated by mixing an incident carrier signal down to a relatively low intermediate frequency signal used in subsequent signal processing, a mixing frequency is selected such that the generated intermediate frequency signal has a frequency offset relative to DC that is substantially that of a single channel spacing between frequency adjacent incident carrier signals, as shown in FIG.,Image rejection is further improved through the integration of a current-driven polyphase filter (,) directly between an input stage (Q,to Q,) and a mixer stage (Q,to Q,) of an image reject mixer (FIG.,) such as to mitigate quadrature divergence between separate in-phase and quadrature paths within the image reject mixer.

Image reject mixer, circuit, and method for image rejection

The invention provides an improved variable capacitance circuit which is substantially linearly controlled using voltage or current control. The circuit comprises two emitter connector transistors and a constant current source or drain forming a current steering circuit. A fixed capacitor is connected to the emitters of the transistors forming a port into the circuit. AC current into the port flows through the fixed capacitor and is fed back through the transistors in a proportion depending on the voltage at their bases. The effective capacitance of the circuit is varied using this variable AC feedback arrangement. Other embodiments use current control to vary the circuit capacitance by varying the effective constant current source level.

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St. Albans, United Kingdom

Peter John Mole