Altera Corporation

Intel Corporation

Peter John McElheny

Irfan Rahim

Richard G Smolen

Girish Venkitachalam

Raminda U Madurawe

Minchang Liang

Che Ta Hsu

Bruce B Pedersen

Shankar Sinha

Shih-Lin S Lee

Fangyun Richter

Yow-Juang W Liu

Francois Gregoire

David Lewis

Vaughn Betz

Aravind Raghavendra Dasu

John C Costello

Dirk Alan Reese

Yowjuang (Bill) Liu

Yow-Juang (Bill) Liu

Jayakannan Jayapalan

Charu Sardana

Priya Selvaraj

Preminder Singh

Jeffrey T Watt

Albert Ratnakumar

Bradley Jensen

Yowjuang Bill Liu

Eric Choong-Yin Chang

Bill Yowjuang Liu

Hai Dang

Kuan Yeow Leong

Yow-Juang(Bill) W Liu

A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.

Active interposer for localized programmable integrated circuit reconfiguration

A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial regions may form source-drain terminals. The edges of the field oxide may be separated from the nearest gate finger edges by a distance that is adjusted automatically with a computer-aided-design tool and that may be larger than the gate-to-gate spacing. Dummy gate finger structures may be provided to ensure desired levels of stress are produced.

Strain-enhanced transistors with adjustable layouts

Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.

Multiport memory element circuitry

A method to design an IC is disclosed to provide a uniform deposition of strain-inducing composites is disclosed. The method to design the IC comprises, determining a total strain-inducing deposition area on an IC design. Then, the total strain inducing deposition area is compared with a predefined size. A dummy diffusion area is modified to increase the total strain-inducing deposition area, when the total strain-inducing deposition area is below the predefined size. Finally, the strain-inducing deposition area is optimized. A method to manufacture the IC and the IC is also disclosed.

Integrated circuit and a method to optimize strain inducing composites

Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.

Integrated circuits with asymmetric transistors

Strain enhanced transistors with adjustable layouts

In an example embodiment, an EDA application creates a physical PCell from a CAD database that relates the physical PCell to a collection of expected mask layers. The EDA application auto-places an identifying text label with the physical and converts the physical PCell and the text label to a format that represents the physical PCell and the text label as sequence of drawn layers. The EDA application generates an equation that performs transformational operations on the drawn layers to create a sequence of derived layers, where the sequence of derived layers defines a collection of logical mask layers. The EDA application executes the equation and compares a derived layer to the expected mask layers, if the derived layer interacts with the derived layer for the text label. If the compared derived layer varies from the expected mask layers, the EDA application reports a variance based on the text label.

Automated verification of transformational operations on a photomask representation

A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Apparatus and methods for adjusting performance of integrated circuits

A memory circuit including a voltage divider with a first phase change memory (PCM) device and a second PCM device coupled to the first PCM device is described. In one embodiment, the first PCM device is in a set resistance state and the second PCM device is in a reset resistance state. Also, in one embodiment, the voltage divider further includes a first switch coupled to the first PCM device and a second switch coupled to the first switch and the second PCM device. In one embodiment, the memory circuit further includes a half latch coupled to the voltage divider and a cascade transistor coupled to the half latch and the voltage divider.

Non-volatile memory circuit including voltage divider with phase change memory devices

Photolithographic reticles are provided that have electrostatic discharge protection features. A photolithographic reticle may be formed from metal structures such as chrome structures on a transparent substrate such as fused silica. Some of the metal structures on the reticle correspond to transistors and other electronic devices on integrated circuits that are fabricated when using the reticles in a step-and-repeat lithography tool. These metal device structures may be susceptible to damage due to electrostatic charge build up during handling of the reticle. To prevent damage, dummy ring structures are formed in the vicinity of device structures. The dummy ring structures may be constructed to be more sensitive to electrostatic discharge than the device structures, so that in the event of an electrostatic discharge, damage is confined to portions of the reticle that are not critical.

Photolithographic reticles with electrostatic discharge protection structures

Growing community of inventors

Morgan Hill, CA, United States of America

Peter John McElheny