Hittite Microwave Corporation

Analog Devices,inc.

Analog Devices Global

Peter John Katzin

Yalcin Alper Eken

Yalcin Ayasli

Marc E Goldfarb

Song Lin

Yusuf Atesal

Abdullah Celik

Michael Patrick Clark

Rosamaria Croughwell

Fatih Kocer

Brian E Bedard

Omar Fathy M Haridy

Ahmed Adel Hassona

Kasim Ayyildiz

Guogong Wang

John C Mahon

Haoyang Yu

An integrated circuit (IC) die is disclosed. The IC die can include a signal via extending through the IC die. The IC die can include a transmission line extending laterally within the IC die in a direction non-parallel to the signal via, the transmission line configured to transfer an electrical signal to the signal via. The IC die can include a matching circuit disposed between the transmission line and the signal via. The matching circuit can include inductance and capacitance matching circuitry to compensate for parasitic inductance and capacitance introduced by transition from the IC die to an underlying carrier.

Matching circuit for integrated circuit die

Provided herein are apparatus and methods for power enhancement of self-biased distributed amplifiers with gate bias networks. By sampling output power a gate bias network with a filter network can adjust gate bias so as to improve the P1 dB compression point and the Psat saturation power level of a self-biased distributed amplifier. Advantageously the filter network can be derived using passive components thereby making it an easy to implement and cost effective approach to improve linearity and output power.

Apparatus and methods for power enhancement of self-biased distributed amplifiers with gate bias networks

A single-ended mixer having a mismatched, high termination impedance is disclosed. The termination impedance can be mismatched by at least one order of magnitude higher than the standard impedance of a given design environment, such as a 50 Ohm environment for a radio frequency (RF) circuit. The termination impedance can be provided in close physical proximity to the mixer core of the single-ended mixer to allow a suitable bandwidth of operation.

Single-ended mixer with reduced loss

Apparatus and methods for reducing glitches in digital step attenuators are disclosed. By configuring a multi-bit DSA such that an attenuation control block changes a plurality of control signals in a manner sequencing individual switches of the DSA, glitches can be reduced and RF signal behavior can be enhanced. The sequence, based upon a unit time delay, causes the transient attenuation value to be bounded between a minimum and maximum and can improve settling time.

Apparatus and methods for reducing glitches in digital step attenuators

An integrated RF switch module including a package customized to include at least one trace. The trace includes one or more of at least one connection pad and at least one landing pad. At least one switching die is connected to the at least one connection pad. At least one device is connected to the at least one landing pad, the at least one device configured to enhance the performance of the switching die.

Integrated switch module

An RF detector configured to provide two outputs, one being a function of the true RMS power level of an RF input signal, and the other being a function of the instantaneous/peak power of the RF input signal, normalized to the average power level. The RF detector includes a variable gain detection subsystem including a single detector or detector array that provides a representation of the power level of the RF input signal. The detector or detector array is common to both the RMS power detection channel and the instantaneous/peak power detection channel of the RF detector. A method of RF detection includes providing representations of the RF input signal at different gain levels, selecting one or more of the representations, and averaging the selected signals. The gain levels of the selected representations is adjusted to provide information about the average power level of the RF input signal.

RF detector with crest factor measurement

A mean square power detector in accordance with one or more embodiments includes a gain or attenuation circuit comprising a plurality of gain or attenuation elements arranged for generating a plurality of amplified or attenuated versions of a radio frequency (RF) input signal. The mean square power detector also includes a plurality of mean square detectors coupled to the gain or attenuation circuit. Each of the mean square detectors receives a different one of the plurality of amplified or attenuated versions of the RF input signal. Each of the plurality of mean square detectors generates an output signal representative of the mean square power of the RF input signal for a different input signal level range. A summing element is coupled to the plurality of mean square detectors for combining the output signals of the plurality of mean square detectors to generate a signal representative of the mean square or root mean square of the RF input signal.

Logarithmic mean-square power detector

An active bias control circuit for an amplifier includes a switch responsive to a supply voltage for providing an input current to the input of the amplifier, and a current sense circuit coupled to the switch for sensing a scaled down replica of the input current to the amplifier. A first amplifier control circuit is responsive to the current sense circuit for adjusting a first control voltage to the amplifier in response to the sensed, scaled down replica of the input current to regulate the input current to the amplifier. Circuitry for power up sequencing an amplifier for an active bias control circuit for the amplifier is also disclosed.

Switched active bias control and power-on sequencing circuit for an amplifier

A variable gain amplifier has at least two branches connected in parallel to drive a common output load. Each branch includes at least two FETs in a cascode configuration. A first FET in each branch is arranged to receive an input signal and to amplify the signal in a common source configuration; the second FET is arranged in a common gate configuration with its source receiving the output current of the first FET. The gate of the second FET is coupled to a corresponding gain control input so that the second FET is enabled when the gate receives an enabling gain control signal and disabled otherwise. Preferably the first and second FETs in each branch are biased in a saturation region of operation when the second FET is enabled by the gain control input. This maintains a low distortion figure throughout the dynamic range of the gain control. Preferably, the invention also includes an active fixed gain power amplification stage for coupling the output to a power amplifier.

Stepped gain controlled RF driver amplifier in CMOS

A post launch identification friend or foe fire control system for a munition has an identification and ranging interrogation unit for mounting on a munition. The interrogation unit transmits an interrogation unit which detects and verifies an incoming identification code from a remote transponder unit in reply to the interrogation code. The range of the remote transponder is determined and a decision signal is provided to the fire control circuit of the munition to enable it to avoid a friendly target; a transponder unit receives the rf carrier signal containing an incoming interrogation code from an interrogation unit on board a munition, validates the incoming interrogation code, and extracts a timing signal from it. An identification code is synchronously generated with the incoming interrogation code using the timing signal. The synchronized identification code is then transmitted back to the interrogation unit on board the munition to confirm the identification of the transponder unit and its range.

Post launch on-board identification friend or foe system

A negative resistance generator includes first and second terminals; first and second inductors connected in series between the terminals; and a semiconductor amplifying device having a first control electrode connected to the first terminal and a first active electrode connected to the second terminal and a second active electrode connected to the junction of the inductors. When employed in an active filter resonator a first variable capacitor is interconnected with the inductors for setting the resonant frequency of the resonator. The resonators may be combined in an active filter with a transmission line where each of the resonators is interconnected to the line by decreasing resistance from the input to the output in order to balance the rf currents to which the resonators are subjected. An improved dual loop active filter control system is achieved by using a master oscillator that employs a resonator that is matched to the active filter resonator in the filter and servoing the frequency and Q-factor controls so that the drive signals are compensated for temperature drifts, manufacturing tolerances, and other problems while a buffer amplifier is used between the master oscillator and the frequency and gain control loops for isolating the master oscillator reference circuit from the loading of the loops and from the perturbation introduced by the frequency reference signal; a frequency shifting circuit in the frequency control loop permits the reference signal to be shifted to a lower or higher frequency than that of the master oscillator.

Active filter resonator and system and negative resistance generator

A switching system for controlling rf energy through an rf transmission medium including a plurality of semiconductor switching devices connected in a series configuration with the primary electrodes connected in series, and means for providing graduated bias on the control electrodes for establishing an equal control voltage on each device between its control electrode and one of its primary electrodes.

Growing community of inventors

Arlington, MA, United States of America

Peter John Katzin