International Business Machines Corporation

Peter John Deacon

Reginald Beer

Carlos Francisco Fuente

William James Scales

Ian David Judd

Barry Douglas Whyte

Neil Morris

Hamish Birrell Williamson Halley

A logic arrangement, method and computer program for reducing incidence of errors in a redundant path system during a process of attachment of a device to a running subsystem, comprises a control component for encapsulating the process of attachment of a device to a running subsystem; a disabling component for disabling a path interface; a testing component for testing for the presence of a usable data path across at least one further path interface; and an enabling component for enabling the at least one further path interface to accept communication with the device responsive to a positive outcome from the testing component; wherein the control component is adapted to permit operation after attachment of the device only if full redundancy is retained. A re-enabling component may re-enable any path interface or further path interface.

Method and apparatus for improved error avoidance in a redundant data path system

In a stacked system, errors detected at a user application interface of one or more host systems are associated with root cause errors at a stack level below a virtualization layer by detecting an error at a user application interface; identifying an associated root cause error at a lower stack level; creating an error trace entry for the error; associating an error log identifier with the error trace entry; making the combined error log identifier and the error trace entry into an error identifier that is unique within the plurality of host systems in said stacked system; and communicating the error identifier to any requester of a service at a user application interface of one or more host systems when the service must be failed because of the root cause error.

Fault tracing in systems with virtualization layers

A data processing system comprises a host computer connected for the transfer of data to and from a plurality of data storage devices arranged in a string, the host computer including communication means comprising first and second ports connecting to first and second communication links, the first and second communication links being connected respectively to first and second data storage devices of said string. A bypassing means is provided between the first and second ports of the host system and the first and second data storage devices, the bypassing means being comprised of an independent bypass circuit on each of the first and second communication links between each of the first and second ports and the first and second data storage devices, the bypassing means being operable to bypass the host computer by connecting the first and second devices only when both of said independent bypass circuits detect a lack of data transfer on their respective links.

Bypass circuit for bypassing host computer which are connected to

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Wimboume, United Kingdom

Peter John Deacon