International Business Machines Corporation

Peter Joel Jenkins

Sebastian Theodore Ventrone

John Atkinson Fifield

Francis A Kampf

Paul Joseph Mattos

Glenn Peter Giacalone

Kenneth Joseph Goodnow

Jason Michael Norman

Raminderpal Singh

Charles E Drake

Mark Beiley

Francis Anthony Creed

A PCI Express compliant method and apparatus for preventing corrupt data being transmitted from a retry buffer of a transmitting component to a receiving component over a PCI Express compliant link. The method including storing parity or electronic error correction bits for each data entry in the retry buffer along with the data itself and then comparing parity or electronic error correction bits generated from a copy of the data from the retry buffer to the parity or electronic error correction bits stored in the retry buffer. If the two sets of bits do not match, a PCI Express link between the transmitting component to a receiving component is forced down.

Method and architecture to prevent corrupt data propagation from a PCI express retry buffer

A method and apparatus for association of multiple PCI Express links with a single PCI Express port. The method includes: connecting a first bus interface component to a second bus interface component with a set of K lanes and set of N lanes, each lane of the set of K lanes and each lane of the set of N lanes consisting of a unidirectional and differentially driven transmitter signal pair and a unidirectional and differentially driven receiver signal pair, wherein K and N are independently whole positive integers equal to or greater than 1.

Association of multiple PCI express links with a single PCI express port

A system provides communication between a plurality of cores in an integrated circuit. The system comprises a circular segmented bus operatively connected to each of the cores for transferring data between the plurality of cores. An arbiter arbitrates which of the plurality of cores can transmit data at any given time.

Reconfigurable circular bus

A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

System and method for correcting timing signals in integrated circuits

A method, program product, and design tool for automatic transmission line selection in application specific integrated circuits. The method includes: determining route paths between blocks of an application specific integrated circuit; scanning the route paths for transmission line replacement candidates; and, for each transmission line replacement candidate, automatically selecting a buffered wire or a transmission line to implement the route path.

Method, program product, and design tool for automatic transmission line selection in application specific integrated circuits

A driver circuit provides for selectively changing the state of an output signal, such as a pre-charged dynamic bus signal. The circuit detects whether or not the data is the opposite state as the pre-charged bus signal, and if so, it drives the bus to the appropriate state. The output from the circuit is self-timed when data can be driven onto the bus as soon as data is valid, i.e., data propagates from the input of the circuit to the bus without depending on a clock or other timing edge.

Self-timed driver circuit

The preferred embodiment of the present invention provides a memory system for use in a computer system that improves the performance of a bit redundancy steering mechanism. The preferred embodiment provides a timing signal path to the bit steering mechanism with a delay shorter than that to the memory data array. Additionally, the required address signals are provided to the bit steering mechanism before the addresses are provided to the memory data array. This is preferably accomplished by bypassing the buffers and providing the address signals directly to the bit steering mechanism.

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Colchester, VT, United States of America

Peter Joel Jenkins