International Business Machines Corporation

Peter Jeffrey Brofman

Kathleen Ann Stalter

Sudipta Kumar Ray

Shaji Farooq

Raymond A Jackson

Mark G Courtney

William Edward Sablinski

John Ulrich Knickerbocker

Hilton T Toy

Lewis Sigmund Goldmann

Patrick Anthony Coico

Scott Ira Langenthal

Gregory Blair Martin

Julien Sylvestre

Karl J Puttlitz, Sr

Kathleen Ann Lidestri

Frank Louis Pompeo

David C Linnell

Li Ming Wang

Wolfgang Sauter

Charles Leon Arvin

Jae-Woong Nah

Gareth Geoffrey Hougham

Jon Alfred Casey

Katsuyuki Sakuma

David L Questad

David L Edwards

Eric D Perfecto

Thomas Anthony Wassick

Krystyna Waleria Semkow

Mario John Interrante

Brian Richard Sundlof

Kamalesh K Srivastava

Ian D Melville

Anson Jay Call

Donald W Henderson

Hsichang Liu

Marie-Claude Paquet

Renee L Weisman

Jeffrey Thomas Coffin

Gregg B Monjeau

Balaram Ghosal

Alexandre Blander

David Clifford Long

William Louis Brodsky

Kamal Kumar Sikka

Jeffrey Allen Zitz

James A Busby

Sushumna Iruvanti

Bruce John Chamberlin

Sarah Huffsmith Knickerbocker

Thomas J Fleischman

Glenn Graham Daves

Herbert I Stoller

Charles L Reynolds

Robin A Susko

Srinivasa S N Reddy

Jason Lee Frankel

Wai Mon Ma

Chon Cheong Lei

Jennifer V Muncy

James H Covell

Jiantao Zheng

Suresh D Kadakia

Martin Beaumier

Horatio Quinones

Kenneth A Bird

Scott A Cummings

Francis F Cappo

Michael J Griffin, Iv

Ellyn M Ingalls

Scott A Sikorski

Mohamed Belazzouz

Shaji Faroog

Timothy W Donahue

Shaji Faroon

Srinivasa Sn Reddy

The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed.

Low-stress dual underfill packaging

A flip chip assembly apparatus includes at least one warpage-suppressor assembly. Each warpage-suppressor assembly can include a side heater, a deformable material pad, and an actuator assembly for moving the side heater and the deformable material pad. Each side heater provides additional heat to peripheral solder balls during bonding of two substrates, thereby facilitating the reflow of the peripheral solder balls. Each deformable material pad contacts, and presses down on, a surface of one of the two substrates under bonding. The deformable material pad(s) can prevent or minimize warpage of the contacted substrate.

Flip chip assembly apparatus employing a warpage-suppressor assembly

In one embodiment of the present invention, inert nano-sized particles having dimensions from 1 nm to 1,000 nm are added into a solder ball. The inert nano-sized particles may comprise metal oxides, metal nitrides, metal carbides, metal borides, etc. The inert nano-sized particles may be a single compound, or may be a metallic material having a coating of a different material. In another embodiment of the present invention, a small quantity of at least one elemental metal that forms stable high melting intermetallic compound with tin is added to a solder ball. The added at least one elemental metal forms precipitates of intermetallic compounds with tin, which are dispersed as fine particles in the solder.

Additives for grain fragmentation in Pb-free Sn-based solder

A chip fabrication method. A provided structure includes: a transistor on a semiconductor substrate, N interconnect layers on the semiconductor substrate and the transistor (N&#x3e;0), and a first dielectric layer on the N interconnect layers. The transistor is electrically coupled to the N interconnect layers. P crack stop regions and Q crack stop regions are formed on the first dielectric layer (P, Q&#x3e;0). The first dielectric layer is sandwiched between the N interconnect layers and a second dielectric layer that is formed on the first dielectric layer. Each P crack stop region is completely surrounded by the first and second dielectric layers. The second dielectric layer is sandwiched between the first dielectric layer and an underfill layer that is formed on the second dielectric layer. Each Q crack stop region is completely surrounded by the first dielectric layer and the underfill layer.

Semiconductor chips with crack stop regions for reducing crack propagation from chip edges/corners

A method attaches a semiconductor chip to a substrate, applies a thermal interface material to a top of the semiconductor chip, and positions a lid over the semiconductor chip typically attached to the substrate with an adhesive. The method applies a force near the distal ends of the lid or substrate to cause a center portion of the lid or substrate to bow away from the semiconductor chip and increases the central thickness of the thermal interface material prior to curing. While the center portion of the lid or substrate is bowed away from the semiconductor chip, the thermal interface material method increases the temperature of the assembly, thus curing the thermal interface material and lid adhesive. After the thermal interface material has and adhesive have cured, the method removes the force from near the distal ends of the lid or substrate to cause the center portion of the lid to return to a position closer to the semiconductor chip, creating a residual compressive stress in the thermal interface material thus improving thermal performance and thermal reliability.

Lid edge capping load

Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.

Methods, apparatus and assemblies for enhancing heat transfer in electronic components using a flexible thermal pillow. The flexible thermal pillow has a thermally conductive material sealed between top and bottom conductive layers, with the bottom layer having a flexible reservoir residing on opposing sides of a central portion of the pillow that has a gap. The pillow may have roughened internal surfaces to increase an internal surface area within the pillow for enhanced heat dissipation. In an electronic assembly, the central portion of the pillow resides between a heat sink and heat-generating component for the thermal coupling there-between. During thermal cycling, the flexible reservoir of the pillow expands to retain thermally conductive material extruded from the gap, and then contracts to force such extruded material back into the gap. An external pressure source may contact the pillow for further forcing the extruded thermally conductive material back into the gap.

Thermal pillow

A pre-thermal reflown dielectric interposer having a plurality of vias traversing through the interposer which correspond to the I/O pads on a chip and substrate. Cone shaped solder elements reside within the vias, whereby these solder elements are cone shaped prior to thermal reflow to permit a reduced force for allowing some non-planarity for joining the chip to the substrate. The interposer may comprise a polyester film, glass, alumina, polyimide, a heat curable polymer or an inorganic powder filler in an organic material. The interposer may also have an adhesive or adhesive layers disposed on the linear surfaces thereof. The present pre-thermal reflown interposer prohibits contact between the solder joints by isolating each of the joints and corresponding bonding pads, as well as preventing over compression of the solder joints by acting as a stand off.

Dielectric interposer for chip to substrate soldering

A silicon based package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Forming via holes which extend through the UTSW, forming metallization in the via holes which extends through the UTSW, making electrical contact to the interconnection structure on the first surface. Then bond the metallization in the via holes to pads of a carrier.

Method of manufacture of silicon based package

A device for preventing short circuits between solder joints in flip chip packaging. The dielectric interposer has a plurality of apertures or vias which correspond to the I/O pads on a chip and substrate. Preferably, the interposer comprises a polyester film, glass, alumina, polyimide, a heat curable polymer or an inorganic powder filler in an organic material. More preferably, the interposer contains an adhesive or has adhesive layers disposed on the linear surfaces of the interposer. Cone shaped solder elements are formed within the apertures of the interposer. The dielectric interposer is positioned between a chip and substrate in an electronic module and thermally reflowed to create an electrical and mechanical interconnection. The interposer prohibits contact between the solder joints by isolating each of the joints and corresponding bonding pads. The interposer also prevents over compression of the solder joints by acting as a stand off.

A module or assembly is formed by interposing a polymer between a carrier and a semiconductor device to be secured to the carrier. The polymer has ionized metallic particles suspended in it. Before setting or curing the polymer, the module is exposed to an electric field which induces migration of the metallic particles to the opposing pads of the carrier and semiconductor device. Such migration ultimately forms metal dendrites extending between mating pad pairs. The dendrites establish a metallurgical bond and conductive paths between the carrier and the overlying semiconductor device. When the polymer is subsequently set, the carrier and device are not only adhered to each other, but the dendrite connections are fixed and structurally reinforced to provide the needed electrically conductive paths.

Method for assembling a carrier and a semiconductor device

A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the present invention are cone shaped and comprise of depositing a first solder followed by a second solder having a lower reflow temperature than the first solder. Warm placement of the electronic component at a somewhat elevated temperature than room temperature but less than the solder reflow temperature reduces the force required during placement of a semiconductor chip to a substrate. After warm placement, reflow of the module occurs at the lower reflow temperature of the second solder. The conical shape of the solder interconnects are formed by a heated coining die which may also coin a portion of the interconnects with flat surfaces for stand-offs. The ability of the cone shaped solder interconnects to meet the opposing surface of a chip or substrate at different heights accommodates the camber typically associated with chip and substrate surfaces.

Process for forming cone shaped solder for chip interconnection

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Hopewell Junction, NY, United States of America

Peter Jeffrey Brofman