S3 Incorporated, Inc.

Exponential Technology, Inc.

Peter J Vigil

James S Blomgren

Earl T Cohen

Jengwei Pan

Hank Lim

Louis S Lederer

A test structure is added to a microprocessor. The test structure is a RAM-like array of scan-clock word lines which selects a row of macrocells to be read or written. Perpendicular to the scan-clock word lines and the rows of macrocells are scan-data bit lines. Each testable macrocell has true and complement signal nodes that are connected to a pair of scan-data bit lines through a pair of n-channel pass transistors. The gates of the pass transistors are controlled by the scan-clock word line. The true and complement signal nodes are the cross-coupled inverters or gates in a latch. The latch is written or loaded by driving opposite data values onto the pair of scan-data bit lines when the pass transistors are activated by the scan-clock word line. The macrocells have random widths and thus do not form regular columns, so the columns of scan-data bit lines must be expanded to accommodate the various macrocell widths. Non-storage macrocells such as logic gates and buffers can be read but not written using the pass transistors connected to true and complement nodes in the macrocell. Reading causes a small voltage difference to be generated on the scan-data bit lines which is sensed by a sense amplifier. Only two n-channel transistors are added to a macrocell to make the macrocell testable. Thus testing is added with minimal area, cost, and delay to the macrocell.

RAM-like test structure superimposed over rows of macrocells with added

A microprocessor die contains several CPU cores that are substantially identical. A large second-level cache on the die is shared among the multiple CPU's. When 3 CPU's are on the die, their outputs are compared during a self-testing mode. If outputs from all three CPU's match, then no error is detected. When two CPU's outputs match, but a third CPU's output mismatches, then the third CPU is faulty. The output compared from each CPU is a serial scan-chain shift-out, parity from internal test points, and a result written to the shared cache. Each CPU core has a serial scan chain. The serial scan chain strings together most flip-flops in the CPU core into a serial chain. A test clock is pulsed to shift out the data from these flip-flops. During each test clock period, the serial data from each CPU is compared to the serial data from other CPU's. Internal test points within each CPU core are defined at high traffic areas in the pipeline. Parity is generated from these internal test points, and the parity from one CPU is compared to that for other CPU's during each CPU clock cycle. The results from each CPU core written back to the shared cache are also compared, and arbitration allows one CPU to write the result to the shared cache while results from other CPU's are discarded. A self-test circuit on the die accumulates errors for each CPU and reports these errors to an inexpensive external tester.

Self-testing multi-processor die with internal compare points

Growing community of inventors

San Jose, CA, United States of America

Peter J Vigil