Qualcomm Incorporated

Rf Magic, Inc.

Entropic Communications, Inc.

Peter J Shah

Guoqing Miao

Matthew David Sienko

Arash Mehrabi

Meysam Azin

Vladimir Aparin

Ankit Srivastava

Rajagopalan Rangarajan

Xiaohong Quan

Wing Fat Andy Lau

Bengt Stefan Gustavsson

Richard Jacques Fortier

Daniel Timothy Gavin

Richard Dominic Wietfeldt

Lalan Jee Mishra

Keith Bargroff

Vijayakumar Dhanasekaran

Shrenik Patel

Seyfollah Seyfollahi Bazarjani

Kwokleung Chan

Taesu Kim

Kyu Woong Hwang

Francesco Gatta

David J Maldonado

Shahin Mehdizad Taleie

Hui-Ya Liao Nelson

Yuanning Yu

Kisun You

Minho Jin

James Ian Jaffee

Martin Alderton

Mohamed Abouzied

Dongjiang Qiao

Siavash Ekbatani

Bert L Fransis

Andrew Puayhoe See

Wenchang Huang

Magesh Hariharan

Gerrit Groenewold

Siva Pavan Kumar Mitnala

Ajay Devadatta Kanetkar

Eunyung Sung

John Michael Murray

YongSik Youn

Vincenzo Filip Andre Peluso

Alexander C Kurylak

Narun Sooppipatt

Iconomos A Koullias

Esa Petri Tarvainen

Carl De Ranter

Certain aspects of the present disclosure generally relate to jamming detection for radio frequency (RF) front-end circuitry. For example, certain aspects provide an apparatus having a first counter configured to count a number of times that a power of a reception signal exceeds a first threshold. The apparatus also includes a second counter configured to count a number of measurements of the power of the reception signal. The apparatus further includes control logic having a first input coupled to an output of the first counter and having a second input coupled to an output of the second counter. The control logic is configured to determine an amount of jamming over a measurement window based on the number of times that the power of the reception signal exceeds the first threshold and on the number of measurements.

Jammer detection system

A system for signal processing includes a radio frequency integrated circuit (RFIC) having a plurality of available transmission paths, the RFIC configured to have at least a first communication signal on a first transmission path of the available transmission paths, a plurality of power amplifier/low noise amplifier (PA/LNA) modules selectively connected to the RFIC, each of the PA/LNA modules configured to connect to at least one respective antenna, and switch logic configured to connect the at least first communication signal to any of the plurality of PA/LNA modules prior to power amplification, while preventing the first communication signal from affecting or being affected by another communication signal on another of the plurality of available transmission paths.

Radio architecture for switching among transmission paths

Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry for a RF power sensor. One aspect is an apparatus including a power sensor transistor configured to receive a radio frequency (RF) input signal and to generate an output indicative of a power of the RF input signal. The apparatus further includes a current source configured to generate a bias current. Also, the apparatus includes a current mirror, which is formed by the power sensor transistor and a second transistor, configured to provide the bias current to the power sensor transistor. The apparatus further includes a feedback circuit, which is coupled to the power sensor transistor and the second transistor, configured to control a drain current of the second transistor with respect to the bias current.

Radio frequency (RF) power sensor

A combined I/Q DAC is provided with a plurality of sources corresponding to a plurality of selectors in which the corresponding source drives the corresponding selector with a source signal to produce a corresponding pair of in-phase and quadrature-phase analog input signals to a summation network. Each selector routes its source signal responsive to a digital value of a corresponding in-phase and quadrature-phase bit pair.

Combined I/Q digital-to-analog converter

A switching mixer array is disclosed for the mixing of a digital LO signal with an analog input signal. Each switching mixer in the array is configured to assume either a first switching state or second switching state responsive to a respective bit of the digital LO signal.

Multiple element mixer with digital local oscillator synthesis

An RF power detector controls an amplitude of a replica input signal so that a power of the replica input signal substantially equals a power of an input signal to the RF power detector. A signal generator generates the replica input signal responsive to a digital control word. A feedback circuit adjusts the digital control word responsive to a comparison of output signals from an analog power sensor.

RF power detector

A circuit includes a first transistor that conducts a first current responsive to a DC bias voltage and an RF signal. A second transistor conducts a second current responsive to the DC bias voltage. The first current and the second current are mirrored through a pair of current mirrors coupled together through a low-pass filter to filter the envelope of the RF signal.

RF square-law circuit

A host integrated circuit is provided with an interrupt aggregator having a signal terminal for coupling to the signal end of an R-2R resistor ladder that has a plurality of rungs corresponding to a plurality of peripheral devices. The interrupt aggregator is configured to process a voltage signal received at the signal terminal to identify any of the peripheral device that intend to trigger an interrupt to a processor.

Digital aggregation of interrupts from peripheral devices

Techniques for detecting the type of a media plug inserted into a corresponding jack. In an exemplary embodiment, the output of a first power amplifier for driving a media plug terminal, e.g., the right headphone or left headphone, is selectively coupled to a reference voltage. Measurements of the voltage at a microphone terminal of the media plug may be alternately made for the reference voltage being at a first value and a second value. In an embodiment, the first power amplifier output voltage may be varied by opening or closing a switch. Alternatively, the first power amplifier output voltage may be directly set by an input voltage to the first power amplifier. By detecting changes in the voltages measured at the microphone terminal, it may be determined whether the media plug is of a North American type or European type.

Plug type detection

A processor is configured to transition in and out of a low-power state at a first rate and to operate in a first mode or a second mode. In a particular method, the processor while coupled to a coder/decoder (CODEC) retrieves audio feature data from a buffer after transitioning out of the low-power state. The CODEC is configured to operate at a second rate in the first mode and at a third rate in the second mode, the second rate and the third rate each greater than the first rate. The audio feature data indicates features of audio data received during the low-power state of the processor. A ratio of CODEC activity to processor activity in the second mode is less than the ratio in the first mode.

Extraction and analysis of buffered audio data using multiple codec rates each greater than a low-power processor rate

An interface unit of a mobile device coupled to an auxiliary device, the interface unit including: a first plurality of switches configured for power delivery to the auxiliary device; at least one isolation unit coupled to the first plurality of switches, the at least one isolation unit configured to isolate the multiple signals and to prevent disruption of data communication between the mobile device and the auxiliary device; and a second plurality of switches configured for the data communication between the mobile device and the auxiliary device, the second plurality of switches configured to bypass the at least one isolation unit.

Mobile device with multiple communication capabilities

A particular apparatus includes a coder/decoder (CODEC) including a first processor and a first buffer. The first processor is configured to analyze audio data samples to detect a keyword. The CODEC is configured to store a set of audio data samples at the first buffer. The apparatus also includes an application processor configured to receive the set of audio data samples from the CODEC via a bus and configured to initialize a speech recognition engine (SRE) based on the set of audio data samples. The application processor is configured to initialize the bus based on an indication from the CODEC that the keyword is detected.

System and method of analyzing audio data samples associated with speech recognition

An apparatus includes an operational amplifier and a plurality of capacitors coupled to an input terminal of the operational amplifier and configured to be selectively coupled to receive one of an input voltage signal and an output voltage signal of the operational amplifier.

Capacitive programmable gain amplifier

Techniques for detecting full insertion of a media plug into a corresponding jack. In an exemplary embodiment, first insertion detection circuitry for detecting the presence of a load is coupled to an innermost terminal of the jack. For North American type audio plugs, the first insertion detection circuitry detects the presence of a left headphone channel coupled to the innermost terminal of the jack. Coupling the insertion detection circuitry to the innermost terminal of the jack advantageously allows detection only when the plug is fully inserted into the jack. Additional detection circuitry may be provided and coupled to the other terminals of the jack. The disclosed techniques may readily be applied to other types of media plugs, e.g., European audio plugs, video plugs, etc.

Plug insertion detection

Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Switch techniques for load sensing

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San Diego, CA, United States of America

Peter J Shah