National Semiconductor Corporation

Entropic Communications, Inc.

Vativ Technologies, Inc.

Peter J Sallaway

Sreen A Raghavan

Thulasinath G Manickam

Abhijit M Phanse

James B Wieser

Tulsi Manickam

Gerard E Taylor

Thomas Clark Bryan

Douglas Easton

Matt Webb

Stewart Webb

A communication system is disclosed that allows high data-rate transmission of data between components. N-bit parallel data is transmitted in K-frequency separated channels on the transmission medium so as to fully take advantage of the overall bandwidth of the transmission medium. As a result, a very high data-rate transmission can be accomplished with low data-bit transmission on individual channels. A transmitter system and a receiver system are described for the communication system.

Low complexity high-speed communications transceiver

A receiver that easily receives signals from transmission channels having long cable lengths is presented. The receiver includes an analog pre-filter that removes distortions and intersymbol interference from a predetermined transmission channel. The analog pre-filter is coupled with a digital receiver that provides digital equalization. The combination of analog equalization with digital equalization allows for simplified digital equalization while retaining the versatility of digital signal processing.

Transceiver system with analog and digital signal echo cancellation having adaptably adjustable filter characteristics

An analog equalizer (and) adaptively equalizes an input analog signal affected with intersymbol interference ('ISI'), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter () converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer () adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder () decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols. Equalization control circuitry (and) adjusts equalization filter characteristics of the equalizers such that adjustments of the filter characteristics of one of the equalizers depend adaptively on adaptive adjustments of the filter characteristics of the other equalizer.

Receiver system with interdependent adaptive analog and digital signal equalization

Analog echo-cancelling circuitry (and) operates on an input analog signal that includes an echo of an output signal, or on an analog signal generated from the input signal, to produce an analog signal with reduced echo. An analog-to-digital converter () converts the echo-reduced analog signal, or an analog signal generated therefrom, into a digital signal. Digital echo-cancelling circuitry (and) operates on the digital signal, or on a digital signal generated therefrom, to produce a digital signal with further reduced echo. An output decoder () decodes the echo-reduced digital signal, or a digital signal generated therefrom, into a stream of symbols. The echo-filtering characteristics of both echo-cancelling circuitries are typically adaptively adjusted during generation of the symbol stream. The analog echo-filtering characteristics may be adapted in response to information provided by operating on the echo-reduced digital signal or on a digital signal generated therefrom.

A receiver for a multi-channel system such as a HDMI system is presented. In accordance with the present invention, the receiver receives one of the plurality of channels and includes an analog portion, a digital-to-analog converter, and a digital control block that provides digital control signals to the analog portion. Equalization can be accomplished partially or wholly in the analog domain and digitally controlled by a digital control loop. A digital equalizer can also be included. A decision feedback equalizer can be implemented that sums an analog output signal into the analog data stream. Timing recovery can be accomplished by digital control of a phase interpolator or delay locked loop that receives a plurality of phases from a timing circuit coupled to receive a clock signal.

High definition multi-media interface

A receiver system contains an analog pre-filter (207 or 619), an analog-to-digital converter (210), a digital equalizer (212), and a decoder (605) arranged sequentially for processing an input analog signal (y). The pre-filter produces a filtered analog signal (Z) with reduced intersymbol interference. The converter provides analog-to-digital signal conversion. Digital equalization circuitry in the equalizer operates according to a transfer frmnction to produce an equalized digital signal (a') as a stream of equalized digital values. Coefficients cand care fixed. Each other coefficient cis adaptively chosen. The decoder converts the equalized digital values, or intermediate values generated therefrom, into a stream of symbols. A receiver system may include two or more receivers each configured in the foregoing way with the digital equalization circuitry in each receiver operating according to a transfer function where at least coefficients c, c, and care non-zero.

Receiver system having analog pre-filter and digital equalizer

An analog equalizer (and) adaptively equalizes an input analog signal affected with intersymbol interference ('ISI'), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter () converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer () adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder () decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols. Equalization control circuitry (and) adjusts equalization filter characteristics of the equalizers such that adjustments of the filter characteristics of the analog equalizer depend adaptively on adaptive adjustments of the filter characteristics of the digital equalizer.

A transceiver according to the present invention receives data from a plurality of frequency separated transmission channels from a complementary transmitter and includes an interference filter for correcting for interference from transmitters other than the complementary transmitter. The interference filter, for example, can correct for near-end cross-talk and echo interference filtering and/or far-end crosstalk interference filtering is presented. A transceiver can include a transmitter portion and a receiver portion with one or more receivers coupled to receives signals in the plurality of frequency separated transmission channels. A baseband transmitter can be combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands). In some embodiments, one baseband PAM transmitter is combined with one or more frequency separated QAM transmitters.

Near-end, far-end and echo cancellers in a multi-channel transceiver system

A sequence detector (-) operating generally according to the Viterbi algorithm contains a branch metric generator (-), comparison circuitry (-), and symbol generation circuitry (, and) for converting digital values of a detector input signal into a sequence of predefined symbols chosen from an alphabet of predefined symbols. The comparison circuitry provides soft output signals for correcting errors. The soft output signals include best and second-best state metrics (p(i) and p(i)) and corresponding best and second-best comparison results (D(i) and D(i)). The symbol generation circuitry typically utilizes the best comparison results to generate a preliminary sequence of the predefined symbols, checks for error in the preliminary sequence, and utilizes the second-best comparison results in correcting any such error in the preliminary sequence so as to convert it into a final sequence of the predefined symbols.

Sequence detector using viterbi algorithm with soft output error correction

A sequence detector (-w) operating generally according to the Viterbi algorithm uses state reduction via division into symbol families to reduce the complexity of sequence detection. The sequence detector contains a branch metric generator (-w), comparison circuitry (-w), and symbol generation circuitry (-w, and) for converting digital values of an input signal into a sequence of symbols chosen from an alphabet of predefined symbols allocated into multiple non-overlapping families each formed with a plurality of the predefined symbols. The branch metric generator makes intra-family branch selections, each of which is one of a plurality of branches respectively corresponding to a family's symbols, and generates corresponding branch metrics. The comparison circuitry determines state metrics and generates corresponding comparison results. The symbol generation circuitry utilizes the comparison results and the branch selections, or selection information generated from the branch selections, to generate the sequence of predefined symbols.

Sequence detector using Viterbi algorithm with reduced complexity sequence detection via state reduction using symbol families

A transceiver system according to the present invention transmits data utilizing the baseband and one or more frequency separated transmission bands. A baseband transmitter is combined with one or more transmitters that transmit data into one of the frequency separated transmission bands. A baseband receiver is combined with one or more receivers that receive data from the frequency separated transmission bands. Any combination of modulation systems can be utilized (e.g. PAM for the baseband and QAM for the frequency separated bands). A transceiver circuit or chip according to the present invention includes a transmitter and a receiver and communicates with a corresponding transceiver chip. In some embodiments, one baseband PAM transmitter is combined with one frequency separated QAM transmitter.

Multi-channel communications transceiver

Disclosed are systems and methods for monitoring and controlling operating modes in a network transceiver. In one embodiment, a computer system is associable with an Ethernet network, and comprises a processing unit, a memory and a transceiver. The transceiver comprises an encoder, a decoder and a controller. The controller controls operating modes of the transceiver, and, specifically, (i) negotiates a communications channel between the computer system and another computer system over the Ethernet network wherein the computer system enters one of a master state and a slave state, and (ii) repeatedly directs, in response to entering the master state or slave state, the encoder to encode data to be transmitted to the another computer in one of an industry-compliant mode and a custom mode until the encoded data is properly received by the other computer.

Systems for monitoring and controlling operating modes in an ethernet transceiver and methods of operating the same

There is disclosed an echo canceller circuit for use in a full duplex transceiver of the type comprising a line driver capable of sending analog transmit signals through a cable and comprising a line receiver capable of receiving analog receive signals from the cable. An echo canceller impedance model circuit is coupled to an output of the line driver and is coupled to an input of the line receiver. The echo canceller impedance model circuit generates an echo canceller current that is equal in magnitude and opposite in phase to a current that represents signal echoes that are present in the analog receive signals. The echo canceller impedance model circuit has a variable impedance for generating the echo canceller current. The variable impedance has at least one variable resistor and at least one variable capacitor. The values of resistance and capacitance in the echo canceller impedance model circuit are varied in response to control signals from a echo canceller control circuit to compensate for and cancel signal echoes.

Growing community of inventors

San Diego, CA, United States of America

Peter J Sallaway