Intel Corporation

Peter J Ruscito

Bret L Toll

Scott Dion Rodgers

Frank Binns

James S Coke

David B Jackson

Masood Tahir

Ves A Naydenov

Shreekant S Thakkar

Robert J Greiner

Pranav H Mehta

Jason W Brandt

Robert N Hasbun

William W Macy, Jr

Eric L Debes

Robert T George

Jonathan D Combs

Sanjoy K Mondal

Jeff C Morriss

Jonathan Jay Tyler

Joann Lam

Narayanan S Iyer

Vesselin Naydenov

Jeff C Morris

Narayana S Iyer

Asad Faizi

A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

Length determination of instruction code with address form field and escape opcode value by evaluating portions other than instruction specific opcode

Determining length of instruction with address form field exclusive of evaluating instruction specific opcode in three byte escape opcode

Determining length of instruction with escape and addressing form bytes without evaluating opcode

Determining length of instruction with multiple byte escape code based on information from other than opcode byte

In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space may have entries that include data values associated with the address space identifier.

Associating address space identifiers with active contexts

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed byte data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed byte data and a second packed byte data. The processor performs operations on data elements in said first packed byte data and said second packed byte data to generate a third packed data in response to receiving an instruction. A plurality of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed byte data.

Method and apparatus for performing multiply-add operations on packed byte data

A method and system are disclosed allowing devices to communicate using a highly efficient low pin count bus comprising a set of data lines, a strobe line, and one control line. Command information is transmitted simultaneously with data, the command information being defined by its timing.

Method and system for implementing control signals on a low pin count bus

An apparatus and method for communication between a host CPU and a security co-processor are disclosed, in which a bus having a bi-directional data and command bus, a bi-directional control line, and a uni-directional clock line, is coupled to the CPU and to the co-processor. The bus supports data transfer between the CPU and the co-processor, including read operations and write operations, where each such operation includes a command phase, a data transfer phase, and an error check phase. The CPU and the co-processor have a dual master slave mode wherein either may be master of the bus, while the other is the slave. The bi-directional data and command bus carries command information from the master to the slave during the command phase, and carries data from the master to the slave during the data transfer phase for a write operation, and from the slave to the master for a read operation. The bi-directional control line specifies the start and end of each transfer. The uni-directional clock line synchronously clocks both the bi-directional data and command bus and the bi-directional control line. Data is transferred a packet at a time; each packet consists of an octet of data, which is transferred during 8 clocks. Flow control need only be applied once for each packet of data, and thus, only once per 8 clocks.

Apparatus and method for multiplexing bi-directional data onto a low pin count bus between a host CPU and co-processor

A flash EEPROM memory array including a cache buffer for storing lines of data being written to all addresses in main memory; a plurality of holding buffers for storing lines of data from the cache buffer addressed to a particular block of addresses in main memory; a plurality of blocks of flash EEPROM main memory for storing lines of data from a holding buffer directed to a particular block of addresses in main memory; and control circuitry for writing lines of data addressed to a particular block of addresses in main memory from the cache buffer to a holding buffer when the cache buffer fills or a holding buffer limit is reached whichever occurs first, writing valid data from an addressed block of flash memory to lines of the holding buffer not holding valid data written from the cache buffer, erasing the addressed block of flash memory, and writing all of the lines in the holding buffer to the addressed block of flash memory.

Flash EEPROM main memory in a computer system

Growing community of inventors

Folsom, CA, United States of America

Peter J Ruscito