Cabletron Systems, Inc.

Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Other

Enterasys Networks, Inc.

Peter J Roman

Robert E Thomas

Wing Cheung

Koichi Tanaka

Kadangode K Ramakrishnan

Michael Ben-Nun

Douglas M Washabaugh

Shinichi Mizuguchi

Anna Charny

Simoni Ben-Michael

Theodore L Ross

Robert J Simcoe

G Paul Koning

Moshe De-Leon

Kohei Abe

Bhupendra Shah

A method and system for requesting an interrupt from a host system to service an adapter connected to the host system and a data interface. Data packets, including one or more data cells, are transferred between the data interface and the host system. The host system includes a host memory that includes a plurality of memory slots to store data packets transferred between the data interface and the host system. It is determined when a transfer of data has resulted in an occurrence of an interrupt event. An interrupt event occurs when the transfer of data includes a transfer of a data cell between the data interface and the host system and the data cell is defined to be an end of a data packet. In response to the occurrence of an interrupt event, it is determined whether to generate an interrupt request to the host system. This step of determining includes determining whether a predetermined interval of time has elapsed since the host system last processed an interrupt request or determining whether a predetermined number of interrupt events have occurred since the host system last processed an interrupt request. If the predetermined interval of time has elapsed or the predetermined number of events has occurred, respectively, the interrupt request from the adapter to the host system is generated.

Method and apparatus for performing TX raw cell status report frequency and interrupt frequency mitigation in a network node

A method of scheduling a plurality of data flows in a shared resource in a computer system, each of the data flows containing a plurality of data cells including the steps of providing a scheduler in the shared resource, initializing the scheduler to receive the plurality of data flows, receiving a first data flow in the scheduler, said first data flow having a first flow rate, receiving a second data flow in the scheduler, said second data flow having a second flow rate, scheduling, by the scheduler, the first data flow and the second data flow such that the first flow rate and the second flow rate are less than an available bandwidth in the shared resource and a relative error is minimized between an actual scheduling time and an ideal scheduling time on a per cell basis, and repeating the steps of receiving and scheduling.

Method and apparatus for relative error scheduling in a communications network using discrete rates and proportional rate scaling

A mechanism for mitigating the rate at which status reports associated with raw cell data transfers occur during receive operations in a network node is presented. The network node has an adapter for coupling a network and a host system, the host system including a host memory. The adapter operates to reassemble cell data received from the network and store the reassembled cell data in the host memory. A raw report holdoff counter is programmed to count a number corresponding to a preselected rx raw report holdoff value. If a raw cell data transfer request to be processed is detected, rx raw report information necessary to creating an rx raw cell status report is copied to a temporary storage area. When the data is transferred to the host system, the raw report holdoff counter is modified by one. When the modified counter has expired, the rx raw report information is written to a report queue in host memory.

Method and apparatus for performing raw cell status report frequency mitigation on receive in a network node

In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further than notification of non-error and maintenance status changes are processed with minimal latency.

Arbitration system based on requester class and relative priority including transmit descriptor valid bit for a shared resource having multiple requesters

A time-based and event-based interrupt frequency mitigation scheme is provided. A holdoff event counter is programmed to count a holdoff event count corresponding to a number of interrupts. A holdoff timer is programmed to time a holdoff interval representing the time period to elapse before the generation of an interrupt request to the host system can occur. When a data transfer request associated with the transfer of data from or to the host system is serviced and results in the occurrence of an interrupt event, the holdoff event counter is modified by one. If either the holdoff event counter or the holdoff timer has expired and the interrupt is enabled, an interrupt request to the host system is generated. In response to such interrupt request generation, the interrupt is processed and both the holdoff event counter and the holdoff timer retriggered.

Method and apparatus for performing interrupt frequency mitigation in a

Method and apparatus for relative error scheduling in a communications

A mechanism for avoiding an initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller to move data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.

Method and apparatus for avoiding control reads in a network node

An apparatus and method for generating a congestion indication bit to be written to the CI field of a backwards RM ATM cell to be transmitted by a network interface utilizes a slot.sub.-- type congestion signal for indicating that the number of slots available for receiving cells is below a threshold limit, and a CI.sub.-- VC signal for indicating that the buffer space consumed by cells received on a particular VC has passed a threshold value. The CI bit in a backward RM cell for the VC when either the slot.sub.-- type congestion signal is set or the CI.sub.-- VC bit is set or the EFCI bit was set in the last data cell received by the network interface or the CI bit was set in the last forward RM cell transmitted by the network interface.

Apparatus and method for setting a congestion indicate bit in an

A method of scheduling the transmission of cells from a network node involves storing entries in a schedule table at predetermined locations, wherein each location represents a point in time at which a cell is to be transmitted. Each entry in the table contains a pointer to a list of virtual circuits having cells scheduled for transmission at the time corresponding to the location of the entry in the table. When a VC has a cell to be transmitted at a particular time, the VC is queued to the head, rather than the tail, of the list of VCs pointed to by the pointer located at the entry in the table corresponding to the time at which the cell is to be transmitted. The VC is therefore the first VC transmitted from the list of VCs.

Apparatus and method for scheduling virtual circuit data for DMA from a

An apparatus and method for transferring data from a source memory (e.g. a host memory) to a peripheral interface via a bus utilizes a transmit buffer memory coupled to the peripheral interface, and a current time counter advancing at the rate at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table data structure stores entries in some or all of its locations, where each location corresponds to a point in time at which data is to be transferred from the transmit buffer memory to the peripheral interface. A schedule table pointer is used for pointing to successive locations in the schedule table. The schedule table pointer advances at a rate faster than the current time counter advances so that the schedule table pointer represents a point in time which is ahead of the point in time currently output by the current time counter. A data transfer is initiated from the source memory to the transmit buffer memory via the bus when a valid entry is stored at the location in the schedule table pointed to by the schedule table pointer. The data is then transferred out of the transmit buffer memory to the peripheral interface when the current time counter reaches the value representing at least the same point in time that was represented by the schedule table pointer when the data transfer was initiated. Data transfers from the transmit buffer memory are thereby synchronized in time with their corresponding entries in the schedule table.

Apparatus and method for performing look-ahead scheduling of DMA

A mechanism by which interrupt frequency mitigation is combined with transmit raw cell status report frequency mitigation is presented. A tx raw cell status report is allowed to occur for only every N raw cell tx slots consumed. When the rate of interrupt requests is mitigated in accordance with holdoff parameters including a holdoff event count corresponding to X interrupt events and a holdoff time interval, and the raw cell status report counts as an interrupt event, an interrupt request is generated for an enabled interrupt if N*X events has occurred or the holdoff time interval has elapsed.

Method and apparatus for performing TX raw cell status report frequency

A method and apparatus for transferring data units between a host memory and a peripheral interface, the data units being subject to a flow control mechanism whereby some of said data units are flow controlled and some of said data units are not. Two transmit buffer memories are coupled to the peripheral interface; one for storing controlled data units to be transferred to the peripheral interface and the other for storing uncontrolled data units to be transferred to the peripheral interface. A single request buffer stores successive requests for data to be transferred from a host memory to either of the two transmit buffer memories. Data transfer circuitry transfers data from the host memory to either of the two transmit buffer memories in response to the requests stored in the request buffer. The data transfer circuitry is prevented from transferring further data from the host memory to the transmit buffer memory storing the controlled data units when it is determined that there is not enough room in the transmit buffer memory storing the controlled data units to accommodate another data unit. The data transfer circuitry is allowed, however, to transfer further data from the host memory to the transmit buffer memory storing the uncontrolled data units.

Transmit data FIFO for flow controlled data

An apparatus and method for transferring data from a source memory to a transmit buffer memory and then from the transmit buffer memory at a particular rate. A current time counter advances at the rate at which data is to be transmitted from the transmit buffer memory to the interface. A schedule memory stores entries, each valid entry being associated with data that is to be transmitted from the transmit buffer memory to the interface. A timestamp is associated with each valid entry in the schedule memory. Circuitry is then operative on each valid entry read from the schedule table to generate a request for a data transfer between the source memory and the transmit buffer memory; perform a data transfer from the source memory to the transmit buffer memory in response to the request; and transfer the data from the transmit buffer memory when the current time circuitry output reaches a value representing at least the same point in time that is represented by the timestamp associated with the entry for which the request was generated.

Apparatus and method for transferring data from a transmit buffer memory

A mechanism for avoiding the initiation of control read transactions on a system bus coupling a host system having a host memory and an interface connected to a peripheral unit as data is moved between the host system and the peripheral unit is presented. Control information associated with data memory portions in host memory is written to the interface for data memory portions storing outgoing data and data memory portions to receive incoming data. The interface includes a controller for moving data between the host memory and the interface by first obtaining the control information for the associated data portions. The interface writes status reports in association with the movement of data between the interface and the host memory via the system bus. The mechanism thus enables data transfers to occur via the system without the initiation of control reads in absence of an exception condition.

In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further that notification of non-error and maintenance status changes are processed with minimal latency.

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Hopkinton, MA, United States of America

Peter J Roman