Lsi Corporation

Agere Systems Inc.

Peter J Nicholas

John Christopher Kriz

Dipankar Bhattacharya

Bernard Lee Morris

Makeshwar Kothandaraman

Carol Ann Huber

Jeffrey Jay Nagy

Antonio M Marques

John A Milinichik

Daniel J Delpero

James John Bradley

A voltage translator circuit () includes an input stage () adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch () adapted for connection to a second voltage supply (VDD) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp () coupled between the input stage () and the latch (). The voltage clamp () is operative to set a maximum voltage across the latch () to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit () generates a first output signal (II) at a junction between the latch () and the voltage clamp (). The voltage translator circuit generates a second output signal () at a junction between the voltage clamp () and the input stage ().

Voltage level translator circuit

Described embodiments provide for a semiconductor device comprising a core and one or more input/output (I/O) buffers surrounding the core. The I/O buffers are adapted to transfer signals associated with core circuitry of the core. The I/O buffers comprise I/O cells having a first orientation and I/O cells having a second orientation. Each I/O cell has a corresponding translator having low voltage transistors in a corresponding footprint. The low voltage transistors in the first orientation I/O cells have the first orientation, and the low voltage transistors in the second orientation I/O cells have the first orientation. The footprints of the first orientation I/O cells and the second orientation I/O cells are compatible with one another.

Orienting voltage translators in input/output buffers

A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

Mode latching buffer circuit

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Philadelphia, PA, United States of America

Peter J Nicholas