International Business Machines Corporation

Peter J Ludlow

Ronald W Knepper

Joseph Anthony Petrosky, Jr

Ralph D Lane

Barry L Moore

A word redundancy scheme for a high speed RAM where the bit output stage uses on-chip logic. An extra emitter on each of the decoders is utilized including redundant word group decoders. A compare circuit has an output to each of the extra emitters and when the address of a bad bit arrives at the compare circuit it de-selects each of the non-redundant decoders at that address and selects the redundant decoders via the extra emitters. Hence, the redundant decoders replace the decoders of the bad bit position.

Word group redundancy scheme

An over current protect circuit for a common bus driver having a complementary pair FET output includes a pair of AND circuits responsive to the gate-source and drain-source voltages for charging separate time integrating capacitors. If a threshold charge is reached a latch is triggered, which in turn disables the driver via a NAND gate and Inverter, and discharges the active capacitor. The latch is reset by dropping the driver enable line. As an alternative, high driver current may be sensed by placing a resistor in series with each output FET and charging the associated capacitor in response to a high current through the resistor.

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Hopewell Junction, NY, United States of America

Peter J Ludlow