Freescale Semiconductor,inc.

Peter J Kuhn

Richard Eguchi

Feng Zhou

Chen He

Ronald J Syzdek

Jon Scott Choy

Gowrishankar L Chindalore

Ko-Min Chang

Fuchen Mu

Thomas Jew

Erwin J Prinz

Paul A Ingersoll

Timothy J Strauss

Horacio P Gasquet

Mohammed Suhail

Thomas S Harp

Richard Kenneth Glaeser

A method of forming a circuitry includes providing a substrate comprising a plurality of die. Each die includes a plurality of resistive random access memory (RRAM) storage cells. The method further includes concurrently initializing substantially all of the RRAM storage cells on the same wafer. Initializing can include applying a voltage potential across the RRAM storage cells.

Circuitry including resistive random access memory storage cells and methods for forming same

In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.

Latent slow bit detection for non-volatile memory

A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.

Threshold voltage techniques for detecting an imminent read failure in a memory array

A method for erasing a non-volatile memory includes: performing a first pre-erase program step on the non-volatile memory; determining that the non-volatile memory failed to program correctly during the first pre-erase program step; performing a first soft program step on the non-volatile memory in response to determining that the non-volatile memory failed to program correctly; determining that the non-volatile memory soft programmed correctly; performing a second pre-erase program step on the non-volatile memory in response to determining that the non-volatile memory soft programmed correctly during the first soft program step; and performing an erase step on the non-volatile memory. The method may be performed using a non-volatile memory controller.

Non-volatile memory (NVM) erase operation with brownout recovery technique

Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests.

Method for simulating long-term performance of a non-volatile memory by exposing the non-volatile memory to heavy-ion radiation

An integrated circuit memory has a plurality of non-volatile memory cells and a reference cell. The reference cell provides a reference current for reading a selected memory cell of the plurality of non-volatile memory cells. A method comprises trimming the reference cell to a predetermined threshold voltage, wherein trimming the reference cell comprises biasing a control gate, a source terminal, a drain terminal, and a substrate terminal of the reference cell with a predetermined set of bias conditions, wherein in response to the predetermined set of bias conditions, the reference cell will gain or lose charge toward an asymptotic state of charge that no longer changes significantly after a predetermined operating time under the predetermined set of bias conditions. In addition, the integrated circuit memory is also configured to adjust the reference cell gate voltage to output a desired target current reference.

Method for electrically trimming an NVM reference cell

A method is provided which includes erasing a first plurality of non-volatile memory bit cells in a memory block comprising a third plurality of memory bit cells during an erase procedure, such that upon completion of the erase procedure, the first plurality of non-volatile memory bit cells are at an erased state. The method also includes programming a second plurality of non-volatile memory bit cells in the memory block during the erase procedure, such that the second plurality of non-volatile memory bit cells is a subset of the third plurality of non-volatile memory bit cells and upon completion of the erase procedure, the second plurality of non-volatile memory bit cells are at a programmed state.

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Austin, TX, United States of America

Peter J Kuhn