Advanced Micro Devices Corporation

Peter J Hannan

Daniel William Bailey

Bradley Gene Burgess

Carlo E Barrientos

Aaron S Rogers

James Joseph Montanaro

Christopher C Sander

Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

Pipeline power gating

A method for constructing a global interconnect model of a device having ambiguous abutments between submodules includes generating a discrete model for each of the submodules, identifying interconnections between the submodules, and defining a plurality of global abutment points for the interconnections between the submodules. Each global abutment point specifies a locus of interconnection points along at least a portion of a boundary of a particular one of the submodules. The discrete models are stitched together based on the global abutment points to construct a global model.

Method and apparatus for constructing a global interconnect model of a device having ambiguous submodule abutments

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Austin, TX, United States of America

Peter J Hannan