Intel Corporation

Peter J DesRosier

Robert F Krick

Dan Wheeler Patterson

Vikram Gupta

Douglas A Guddat

Glenn F King

Tim Lambert

James S Chung

Sridhar Jayaraman

Navin Saxena

Silvio Picano

An embodiment of the present invention is a technique to provide a parallel test mode for multi-core processors. A test access port (TAP) in a first processor core generates a first test data output (TDO) from a first test data input (TDI) or a first delayed TDI according to a TDO select bit. The first delayed TDI is clocked by a test clock (TCK). The first processor core has a first core circuit. The TAP generates a phase select word. A clock generator generates a clock signal synchronized with the TCK and has a low phase and a high phase. A first enable circuit enables first core data from the first core circuit in one of the low and high phases of the clock signal according to the phase select word.

Parallel test mode for multi-core processors

An electronic component for failure detection and analysis of bus activity comprises configuration circuitry, a buffer, and read circuitry. The configuration circuitry, the buffer, the read circuitry and the bus being tracked are on the same die. The configuration circuitry identifies one or more modes, one or more triggers, and one or more responses associated with the triggers. The buffer stores transactions on a bus according to the configuration circuitry. The read circuitry reads data from the buffer. A method of tracking bus activity comprises configuring a bus activity tracking component; monitoring an interface for a trigger event; and performing associated responses upon the occurrence of the trigger event.

Method and apparatus for bus activity tracking

A method and apparatus for software controlled timing of embedded memory includes an embedded memory array and input/output (I/O) control circuitry coupled to the embedded memory array. The I/O control circuitry provides a plurality of I/O signals to the embedded memory array to control the input of data to the embedded memory array and output of data from the embedded memory array. The I/O control circuitry also includes programmable delay circuitry to alter the timing of the I/O signals.

Method and apparatus for software controlled timing of embedded memory

A processor with a built in self test function that provides intermediate self test results is disclosed including at least one logic array and a test circuit for each logic array coupled to generate a logic array signature during a built in self test of the processor. The processor further comprises a set of internal registers including a performance register that stores the logic array signature and a register that stores a pass/fail indication for the built in self test of the processor. The internal registers also store a pass/fail indication for a cache memory built in self test and a pass/fail indication for a constant read only memory built in self test.

Built-in self test function for a processor including intermediate test

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Portland, OR, United States of America

Peter J DesRosier