International Business Machines Corporation

Peter J Camporese

Howard Harold Smith

Allan Harvey Dansky

Kwok Fai Eng

Wiren Dale Becker

Alina Deutsch

Dale E Hoffman

Bhupindra Singh

Phillip John Restle

Timothy Gerard McNamara

David Allan Webber

Patrick James Meaney

Leon Jacob Sigal

Richard Frank Rizzolo

Patrick M Williams

Michael Alexander Bowen

Adam R Jatkowski

Brian J O'Leary

Keith G Barkley

Robert P Dwyer

A method (and a system for using the method) for automating a slew rate analysis between two or more circuits on a semiconductor chip. The method includes the steps of: receiving as input one or more input parameters characterizing the physical medium through which the signal propagation occurs (the net) and the electrical characteristics of signals transmitted between the circuits; and providing as output one or more output parameters characterizing the appropriate solution for physical implementation of the circuit(s) and net(s) which satisfy the performance requirements of the system. The receiving step can comprise any one of: providing a hierarchical signal name cross-reference defining a name for the signal for a given hierarchy level of the circuits; providing a set of one or more boolean equations used to generate the one or more output parameters from the one or more input parameters; providing a physical design information for the circuits; and providing a timing information for the signals. The boolean equations can include as input variables: the physical design information for the circuits; and the timing information for the signals. The transmitting step includes the steps of: determining if the signals require one or more buffers; determining if signal pin locations of the circuits through hierarchical levels thereof are not optimal; determining if strengths of transistors driving the signals must be increased; determining if the widths of wires used to transmit the signals must be increased; and determining if wires used to transmit the signals must be on less resistive wiring layers.

Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI design

A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.

Method for evaluating decoupling capacitor placement for VLSI chips

Deterministic evaluation of coupling noise voltage is a function of many physical and electrical parameters such as wiring level, widths, spacing, net topologies, drv impedance and slew rates. This evaluation requires electrical modeling and subsequent circuit simulation to assess the sensitivities of these parameters. These sensitivities can be categorized as coupling guidelines that can be directly linked through extracted physical design data. This invention discloses the development and implementation of a technique for using a coupling guideline table early in the design of an integrated circuit when all the parameters generally required for coupling noise voltage calculations are not available. The steps include: creating a flat wire routing map of the integrated circuit, identifying the coupled wire segments on the integrated circuit, tracking wire interconnection patterns on the integrated circuit, deriving electrical parameters for the coupled wire segments, and generating a coupling guideline table with parameters for a plurality of electrical parameters. The parameters in the coupling guideline table are applied to the derived electrical parameters and a report is generated that lists the derived electrical parameters that fail to comply with the parameters in the coupling guideline table.

Method for performing coupling analysis

A method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, begins by defining a size for the chip of a hierarchical design, and then removing blocked areas, including clock and power grid areas leaving the wiring channels available for interconnecting the individual elements of the VLSI chip. A percentage of the available area is allocated for wiring levels for global and local wiring as parallel iterations for the global and local wiring proceed and modified as the parallel iterations for the global and local wiring progress. During the parallel iterative process the number of wires increases for the power grid area to prevent a signal wire from having an active wire on either side of the signal wire. In the interactive process, a vertical slice of wiring resources used for the space above a macro entity is defined and the macro entity is checked with the context of the VLSI chip physical design above it. The process employs a blockage modeling tool to accurately wire DRC correct wiring designs using automatic routing tools.

Contract methodology for concurrent hierarchical design

A routing program length method for positioning unit pins in a hierarchically designed VLSI chip first identifies unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a &ldquo;flat&rdquo; file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the Incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value a router program is run in isolation against each net without unit pins. Pins are placed where the wiring route for the net crosses each unit boundary.

Routing program method for positioning unit pins in a hierarchically designed VLSI chip

A method for identifying and positioning sub-optimally positioned unit pins in a hierarchically designed VSLI chip without modifying unit placement, comprising: generating a flat data file, generating a first pin log using the flat data file including data for unit pins and for macro pins of a net, generating a second pin log using the flat data file including data for macro pins of the net, determining a minimal net length using the first pin log and determining a minimum net length using the second pin log, calculating the difference between the minimal net length determined using the first ping log and the minimal net length determmed using the second pin log, identifying sub-optimally positioned unit pins by comparing the calculated difference to a threshold, and repositioning the identified sub-optimally positioned unit pins.

Minimal length method for positioning unit pins in a hierarchically designed VLSI chip

A method for identifying unit pin positions initially assigned in a hierarchical VLSI design that, if implemented, would increase the net length of the net of which the unit pins are a part. To identify unit pins, where the unit pin position assigned by the unit designer turns out to be a poor choice of position when the unit is integrated into the top level design, a &ldquo;flat&rdquo; file is created of the completed VLSI design with the units positioned on the chip, including their pin placements as assigned by the unit designers. The flat file includes not only top level unit data and unit-to-unit net data, but also macro data and macro net data integral to each unit design. The flat design data file is used to generate two pin logs; one pin log includes the incremental lengths of each net including the incremental lengths associated with the unit pins (if any) assigned by the designers of the units. The other pin log is the same, except it does not include the unit pins and the incremental net length associated with the unit pins. A commercially available program, for example, a Minimum Spanning Tree (MST) program or a Steiner Minimal Tree program is run against every net; once against the nets in the pin log list that includes the pins assigned by the designers of the units, and once against the nets in the pin log list that does not include assigned unit pins. The output of interest of the MST (or similar program) run against the net files with and without pin assignments is a text file containing the net names, number of pins per net with and without unit pins and the difference between the net lengths with and without unit pin assignments. If the difference exceeds a threshold value, that net is identified so that the unit pins can be reassigned by the unit designer or designers.

Method to identify unit pins that are not optimally positioned in a hierarchically designed VLSI chip

A method (and a system for using the method) for placing a semiconductor circuit device between a driver and one or more receivers on the floor space of a chip. The method includes the steps of: determining respective distances between the driver and each of the one or more receivers; determining a shortest of the distances; determining midpoint along the shortest distance; determining whether the midpoint is predesignated to the floor space of one or more blocking semiconductor circuit devices; placing the repeater at the midpoint if the midpoint is not predesignated to the one or more blocking semiconductor circuit devices; and applying a backoff algorithm to incrementally back away from the midpoint to an optimal location, and placing the repeater at the optimal location, if the midpoint is predesignated to the one or more blocking semiconductor circuit devices. The method can also include the steps of: determining whether the to be placed semiconductor circuit device can be placed at a set of incremental locations located along one or more axes away from the midpoint; and placing the to be placed semiconductor circuit device at one of the one or more acceptable incremental locations. The step of determining the set of incremental locations can be performed in a spiral pattern away from the midpoint. The semiconductor circuit device to be placed can be, for example, a repeater along the path of a net (length of wire) to regenerate a propagated signal.

Method for automating the placement of a repeater device in an optimal location, considering pre-defined blockages, in high frequency very large scale integration/ultra large scale integration (VLSI/ULSI) electronic designs

An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid. Electrical simulation models are created for network components and clustered grid loads are substituted with smoothed clustered grid loads. A set of N,electrical net lists are next created by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors. Each N,electrical net list is then tuned, wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of each N,electrical net list.

X-Y grid tree clock distribution network with tunable tree and grid networks

X-Y grid tree tuning method

A clock tuning system and method for a data processing system with enhanced timing failure diagnostics and unlayering capabilities. Both common and individual phase adjusting capabilities ensure programmable tuning of clock pulses distributed throughout a computer system, thereby facilitating isolation of timing margin failure to specific clock signals or enhancing system performance by shifting timing margin between logic paths. Both single-clock and dual-clock data processing are discussed, as well as clock tuning embodiments for each.

Growing community of inventors

Hopewell Junction, NY, United States of America

Peter J Camporese