Intel Corporation

Peter J Barry

Debendra Das Sharma

David J Harriman

Robert G Blankenship

Mahesh U Wagh

Mark B Rosenbluth

Jasmin Ajanovic

Scott Dion Rodgers

Anil Vasudevan

Prashant Sethi

Ilan Pardo

Sridhar Muthrasanallur

Ajay V Bhatt

James E Akiyama

Eran Tamari

Doron Shamia

Eliezer Weissmann

Ohad Falik

Abraham Mendelson

Avi Mendelson

Avi (Abraham) Mendelson

Vincent J Zimmer

Rajesh Poornachandran

Gopinatth Selvaraje

Lee G Rosenbaum

Arjan Van De Ven

Julien Carreno

Peter A Dice

Mark Y Kelly

Keith Nolan

Donald F Hooper

Michael J Nolan

Niall Cahill

Keith A Ellis

Cliodhna Ni Scanaill

Jessica C McCarthy

Hugh Martin Carr

Charlie Sheridan

Brian McCarson

Praveen B Mosur

Gabriel Mullarkey

Ohad Fallk

Ellezer Weissmann

Avi (Arraham) Mendelson

Julien CARREÑO

Orchestration and/or management of services on deployed computing, electronic, appliance and like devices are described. A service orchestration and/or management system ('SOMS') may be configured to provide for orchestration and/or management of services to one or more deployed devices. The SOMS may obtain information from deployed devices, such as status, capabilities and service metadata. The SOMS may then encapsulate and store the obtained information for later use. The SOMS may also store service information, facilitate creation of services based on stored service definition meta-data, modeling or simulating a service prior to deployment, and deployment of a service to remotely deployed devices followed by activation to begin operation of the service. Other embodiments may be described and claimed.

Orchestration and management of services to deployed devices

In an embodiment, a system on a chip includes: a single core to execute a legacy instruction set, the single core configured to enter a system management mode (SMM) to provide a trusted execution environment to perform at least one secure operation; and a memory controller coupled to the single core, the memory controller to interface with a system memory, where a portion of the system memory comprises a secure memory for the SMM, and the single core is to authenticate and execute a boot firmware, and pass control to the SMM to obtain a key pair from a protected storage and store the key pair in the secure memory. Other embodiments are described and claimed.

Providing a trusted execution environment using a processor

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Atomic operations in PCI express

Transaction layer packet formatting

PCI express transaction descriptor

Transaction re-ordering

Prefectching in PCI express

Atomic operations

A system apparatus and method for supporting one or more functions in an IO virtualization environment. One or more threads are dynamically associated with, and executing on behalf of, one or more functions in a device.

Dynamic association and disassociation of threads to device functions based on requestor identification

PCI express enhancements and extensions

PCI express enhancements and extensions including device window caching

Growing community of inventors

Ardncrusha, Ireland

Peter J Barry