Seagate Technology Incorporated

Peter Igorevich Vasiliev

Clifton James Williamson

Bernardo Rub

Richard Martin Born

Gregory Lee Silvus

Thomas V Souvignier

Cenk Argon

Timothy Richard Feldman

Jonathan Williams Haines

James Joseph Touchton

Prafulla Bollampalli Reddy

Jimmie Ray Shaver

Brett Alan Cook

Robert D Cronch

Hui Su

Kenneth R Burns

Gary W Reininga

Gabriel Ibarra

Mary Elizabeth Dunn

Wuping Chen

Kavi Alptekin

Srinivas Maddali

Values are grouped into a first set of groupings of values. Based on inner codes, the number of groupings in the first set of groupings that have at least one erroneous value is determined. If the number of groupings in the first set of groupings that have an erroneous value is fewer than a maximum number of groupings that can be corrected by outer codes, a seek operation is begun. During the seek operation, the outer codes are used to detect and correct the erroneous values that were produced during the reading of values. In other aspects, a parity section for a data section of a data storage device is dirtied before writing any data to the data section such that if writing to the data section is interrupted, the parity section will indicate that it should not be used to correct data read from the data section.

Outer code error correction

The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, 'transformed' EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.

Computing an error detection code syndrome based on a correction pattern

Methods and systems are disclosed to generate a data map for a data storage device. A data map may be generated by scanning, during a power-on initialization process, data units of data stored on a data storage medium of a data storage device. The scanning may start from a selected data unit and proceed through the data units in an order opposite to a write order to identify a first data unit that is not fully erased. Also. an error recovery status of the first data unit may be determined based on an error correction code. A likely erased status of the first data unit may be assigned when the determined error recovery status is unrecoverable.

Data storage devices and methods for power-on initialization

An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Interleaver with linear feedback shift register

The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, 'transformed' EDC syndromes are computed during the read back of data and parity from the medium. The transformed syndromes are values of the polynomial whose coefficients occur in reverse order from that of the EDC codeword polynomial. In essence, by reversing the order of the coefficients, the Chien search processes the terms in descending order which is the right direction for Horner evaluation.

Method and apparatus for error detection

Low complexity pseudo-random interleaver

A second stage SOVA detector comprises a dynamic state reordering block with inputs that receive absolute state domain data from a first stage SOVA detector. The second stage SOVA detector provides relative state domain data outputs and selection bit outputs. The second stage SOVA detector comprises pipeline registers. The pipeline registers receive the relative state domain data outputs and the selection bit outputs and provide pipelined outputs. The second stage SOVA detector comprises a reliability update-register exchange unit receiving the pipelined outputs and providing detected data bits and reliabilities.

Second stage SOVA detector

Embodiments of the present invention illustrate various configurations of a channel-to-controller interface. In one embodiment, width of symbols crossing the interface is fixed, as is the clock rate. In other embodiments, the symbol width is variable, and the clock rate is also varied based upon the size of the interface symbol width and the operation of the channel.

Configuration of channel-to-controller interface in a disc drive

The invention relates to apparatus and method that provide an improved media codeword and which can distinguish an uncorrectable data error from a wrong block address error and permit the address to be recovered from readback data. In accordance with one embodiment of the invention, method for generating parity is provided in which a sequences representing address and data are received. The address sequence is multiplied by a set of multiplier symbols to generate a first sequence of product symbols. A first portion is added to the data sequence prior to generating a first parity sequence and second portion is added directly to the first parity sequence to generate the final parity sequence. A corresponding method of generating syndromes from readback data is provided. System and apparatus incorporating the inventive method are also provided.

Physical block address recovery apparatus system and method for cyclic error correction codes

Growing community of inventors

Longmont, CO, United States of America

Peter Igorevich Vasiliev