International Business Machines Corporation

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Peter I Smeys

Norman Jay Rohrer

Michael John Hargrove

Fariborz Assaderaghi

Jack Allan Mandelman

Paul David Agnello

Bruce Bennett Doris

Anthony K Stamper

Effendi Leobandung

James William Adkisson

Kerry Bernstein

Subramanian Srikanteswara Iyer

Omer H Dokumaci

Chandrasekhar Narayan

Klaus D Beyer

Edward P Maciejewski

Axel Christoph Brintzinger

Sundar Kumar Iyer

Patricia A O'Neil

Isabel Ying Yang

Deborah A Ryan

In an integrated circuit process for SOI including trench device isolation, the problem of voids in the trench fill is addressed by a triple fill process, in which a thermal oxide sidewall having recesses at the bottom corners is covered with a LPCVD deposition that fills in the recesses, followed by a void-free HDP deposition. Densification results in substantially the same etch rate for the three types of oxide.

Triple oxide fill for trench isolation

Thermal degradation of a low-k organic dielectric material is avoided or limited in the proximity of a heat source such as a fusible element by overlaying the low-k material with a thermally conductive material and providing a low thermal resistance path from the thermally conductive material, possibly having a low modulus of elasticity, to a heat sink. The thermally conductive material thus provides crack-stop protection for further layers of an integrated circuit or interconnect structure above the fusible element by mechanical, chemical and thermal encapsulation of the heat source and low-k material.

Fuse structure with thermal and crack-stop protection

A method of forming a silicon on insulator (SOI) body contact at a pair of field effect transistors (FETs), a sense amplifier including a balanced pair of such FETs and a RAM including the sense amplifiers. A pair of gates are formed on a SOI silicon surface layer. A dielectric bridge is formed between a pair of gates when sidewall spacers are formed along the gates. Source/drain (S/D) conduction regions are formed in the SOI surface layer adjacent the sidewalls at the pair of gates. The dielectric bridge blocks selectively formation of S/D conduction regions. A passivating layer is formed over the pair of gates and the dielectric bridge. Contacts are opened partially through the passivation layer. Then, a body contact is opened through the bridge to SOI surface layer and a body contact diffusion is formed. Contact openings are completed through the passivation layer at the S/D diffusions. Tungsten studs are formed in the contact openings.

Pair of FETs including a shared SOI body contact and the method of forming the FETs

A method for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a first planarizing organic film on the gate dielectric material and abutting vertical sidewalls of the patterned gate stacks, said planarizing organic film not being present on top, horizontal surfaces of each of the patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and first planarizing organic film and forming a second planarizing organic film and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by said second resist; and removing the second resist and the second planarizing organic film.

Anti-spacer structure for self-aligned independent gate implantation

A circuit for maintaining the threshold voltages of transistors implemented in a dynamic CMOS circuit. A plurality of transistors have source drain connections connected between the body contacts of transistors in the dynamic CMOS circuits, and the constant voltage potential. When operating the dynamic CMOS circuit in the precharge phase, the body of each of the CMOS circuit transistors is maintained at the constant voltage potential. During the evaluate phase, the body potential is permitted to float to its precharge state. The initial reference level voltage established during a precharge phase maintains the transistor gate-source threshold voltage at a constant value, eliminating both bipolar effects and history effects which accompanying a changing body potential.

SOI CMOS dynamic circuits having threshold voltage control

A method for forming source/drain extensions with gate overlap. An oxide layer is formed on a semiconductor substrate and a gate structure on the semiconductor substrate. First, sidewall spacer regions are formed on sides of the gate structure. Second spacer regions are formed on sides of the sidewall spacer regions. Upper regions of the gate structure and the sidewall spacer regions are silicided. Portions of source and drain extension regions in the semiconductor substrate adjacent the gate structure are also silicided.

Semiconductor device with abrupt source/drain extensions with controllable gate electrode overlap

A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.

Electrical fuses employing reverse biasing to enhance programming

Method for fabricating abrupt source/drain extensions with controllable gate electrode overlap

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White Plains, NY, United States of America

Peter I Smeys