Alcatel N.v.

Peter I Barri

Jan L De Groote

Martin L De Prycker

Mark L Ryckebusch

Luc O Beyne

Communication switching element (SE) with a plurality of input receiver circuits (RC01/16), a plurality of output transmitter circuits (TC01/17), and a plurality of control circuits (CMC01/08) each with a data write bus (DB01/08), with a plurality of data buffers (DB0101/1601); DB0108/1608) coupling the input circuits to the data bus, and with a plurality of RAMs (RAM0101/1701; RAM0108/1708) each with an input individually connected to the data write bus and with an output individually connected to a respective one of the output circuits.

Communication switching element

Communication process and switching element for carrying out this process

Communication switching system

An asynchronous time division communication system having at least one station including a buffer and an associated processor for writing data packets into said buffer at a sending clock frequency, and for reading data packets from said buffer at a receiving clock frequency. The processor is further capable of assessing the real packet filling level of the buffer and adjusting the receiving clock frequency in corresponding relationship to the assessed real packet filling level. The processor calculates a mean packet filling level after a measured time has elapsed by using the mean of m successively assessed real packet filling levels of said buffer and using the calculated mean packet filling level for adjusting the receiving clock frequency.

Asynchronous time division communication system

A switching network including one or more switching circuits and a control circuit (CCC), the switching circuit including a time division switching element (SR12-SR78) provided with inputs and outputs for data packets and the switching element being controlled by the control circuit (CCC). This switching element is constituted by a closed loop shift register (SR12-SR78) of which all the stages are controlled by a clock signal (f2) provided by the control circuit (CCC) and form a number of shift register portions (SR12-SR78) which are each (SR12) associated to a parallel input (h12) having access to all stages of this portion. A plurality of inputs (R1/2) of the switching element have access to this parallel input (h12) via a multiplexer (MUX12).

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Bonheiden, Belgium

Peter I Barri