International Business Machines Corporation

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Peter I A Barri

Jean Louis Calvignac

Joseph Franklin Logan

Claude Basso

Brahmanand Kumar Gorti

Johan G A Verkinderen

Fabrice Jean Verplanken

Natarajan Vaidhyanathan

Marco C Heddes

Miroslav Vrana

Alex M M Niemegeers

Natarajan Valdhyanathan

Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.

Frame alteration logic for network processors

A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

Apparatus and method for efficiently sharing memory bandwidth in a network processor

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Bonheiden, Belgium

Peter I A Barri