Infineon Technologies Ag

Intel Mobile Communications Gmbh

Peter Huber

Martin Ostermayr

Stephan Henzler

Christian Pacha

Joel Hatsch

Siegmar Koeppe

Ettore Amirante

Thomas Baumann

Thomas Nirschl

Thomas Kuenemund

Thomas Fischer

Winfried Kamp

Yannick Martelloni

Karl Hofmann

Michel d'Argouges

In various embodiments, a memory device includes at least one memory cell and at least one virtual supply line coupled to the at least one memory cell. The memory device is designed in such a way that a voltage potential present on the virtual supply line is altered after an active access to the memory cell by virtue of a charge stored within the memory device during the active access being re-stored in such a way that a state of the memory cell with a reduced leakage current consumption is achieved.

Memory device and method for putting a memory cell into a state with a reduced leakage current consumption

A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another.

Identification circuit and method for generating an identification bit

Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a '1' or '0' under normal read/write conditions, aspects of the present discloser relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, &#x201c;weak&#x201d; memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells.

Memory reliability verification techniques

The present disclosure relates to on-chip self calibrating delay monitoring circuitry.

On-chip self calibrating delay monitoring circuitry

A system for terminating a homogenous cell array is disclosed. A preferred embodiment comprises a plurality of homogenous cells arranged in rows and columns to form the homogenous cell array, wherein a first homogenous cell of each column is electrically differently connected than a rest of the homogenous cells of the column.

Homogenous cell array

Implementations are presented herein that relate to a memory cell, a memory device, a device and a method of accessing a memory cell.

Memory cell, memory device, device and method of accessing a memory cell

A memory system and method are described. For example, a memory cell includes a capacitance and an access circuit in association with the capacitance and having an access circuit terminal. The memory cell further includes a voltage control unit to adjust a potential at the access circuit terminal in a retention state such that a retention time of the memory cell is increased. A method of operating a memory cell includes, for example, adjusting a potential at an access circuit terminal of the memory cell to increase a retention time.

Method of operating a memory cell, memory cell and memory unit

A memory cell includes transistors and two read ports. Each read port is configured to be connected to a read line. The memory cell is configured such that in a read operation of the memory cell an information stored in the memory cell is readable by a differential reading including an evaluation of an electric current between the two read ports.

Growing community of inventors

Neubiberg, Germany

Peter Huber