International Business Machines Corporation

Peter Howland Oden

Daniel Arthur Prener

Ravi Nair

Kathryn Mary O'Brien

John Kevin O'Brien

Erik Richter Altman

Sumedh Wasudeo Sathaye

Allan Mark Hartstein

Thomas R Puzak

Mark Jay Charney

Vijayalakshmi Srinivasan

Sumeda Wasudeo Sathaye

A method (and system) of emulation in a multiprocessor system, includes performing an emulation in which a host multiprocessing system of the multiprocessor system supports a weak consistency model, and the target multiprocessing system of the multiprocessor system supports a strong consistency model.

Method and system for efficient emulation of multiprocessor memory consistency

A method (and structure) of mapping a memory addressing of a multiprocessing system when it is emulated using a virtual memory addressing of another multiprocessing system includes accessing a local lookaside table (LLT) on a target processor with a target virtual memory address. Whether there is a 'miss' in the LLT is determined and, with the miss determined in the LLT, a lock for a global page table is obtained.

Method and system for efficient emulation of multiprocessor address translation on a multiprocessor

In a host system, a method for using instruction scheduling to efficiently emulate the operation of a target computing system includes preparing, on the host system, an instruction sequence to interpret an instruction written for execution on the target computing system. An instruction scheduling on the instruction sequence is performed, to achieve an efficient instruction level parallelism, for the host system. A separate and independent instruction sequence is inserted, which, when executed simultaneously with the instruction sequence, performs to copy to a separate location a minimum instruction sequence necessary to execute an intent of an interpreted target instruction, the interpreted target instruction being a translation; and modifies the interpreter code such that a next interpretation of the target instruction results in execution of the translated version, thereby removing execution of interpreter overhead.

Hybrid mechanism for more efficient emulation and method therefor

A method (and system) for performing an emulation of an operation of a target computing system, includes interpreting a target instruction, recognizing an unused capacity of a host system when the host system is interpreting the instruction, and performing a translation of the instruction without increasing a time of interpreting the instruction.

A method (and system) for emulating a target system's memory addressing using a virtual-to-real memory mapping mechanism of a host multiprocessor system's operating system, includes inputting a target virtual memory address into a simulated page table to obtain a host virtual memory address. The target system is oblivious to the software it is running on.

Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host

A method (and system) for executing a multiprocessor program written for a target instruction set architecture on a host computing system having a plurality of processors designed to process instructions of a second instruction set architecture, includes representing each portion of the program designed to run on a processor of the target computing system as one or more program threads to be executed on the host computing system.

Method and system for multiprocessor emulation on a multiprocessor host system

A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while instructions that are predicted as not useful are discarded. The prediction regarding the usefulness of a prefetching instructions is performed utilizing a branch prediction mask contained in the branch history mechanism. This mask is compared to information contained in the prefetching instruction that records the branch path between the prefetching instruction and actual use of the data. Both instructions and data can be prefetched using this mechanism.

Prefetching using future branch path information derived from branch prediction

A method (and system) of transparent dynamic optimization in a multiprocessing environment, includes monitoring execution of an application on a first processor with an execution monitor running on another processor of the system, and transparently optimizing one or more segments of the original application with a runtime optimizer executing on the another processor of the system.

Method and system for transparent dynamic optimization in a multiprocessing environment

A mechanism is described that prefetches instructions and data into the cache using a branch instruction as a prefetch trigger. The prefetch is initiated if the predicted execution path after the branch instruction matches the previously seen execution path. This match of the execution paths is determined using a branch history queue that records the branch outcomes (taken/not taken) of the branches in the program. For each branch in this queue, a branch history mask records the outcomes of the next N branches and serves as an encoding of the execution path following the branch instruction. The branch instruction along with the mask is associated with a prefetch address (instruction or data address) and is used for triggering prefetches in the future when the branch is executed again. A mechanism is also described to improve the timeliness of a prefetch by suitably adjusting the value of N after observing the usefulness of the prefetched instructions or data.

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Ossining, NY, United States of America

Peter Howland Oden