Infineon Technologies Ag

Peter Hober

Knut Just

Christian Jenkner

Xiaoning Nie

A circuit arrangement is provided comprising a first partial circuit to receive a supply voltage, a second partial circuit to receive an output signal of the first partial circuit and a first clock signal, the second partial circuit to store the output signal of the first partial circuit depending on the first clock signal, and a control unit to decouple the supply voltage from the first partial circuit for a time period that is shorter than a cycle duration of the first clock signal, wherein the control unit is configured to receive a second clock signal which is derived from the first clock signal by delaying.

Circuit arrangement and method of operating a circuit arrangement

One embodiment of the invention provides a circuit. The circuit includes a switching unit configured to connect or disconnect a voltage domain to a supply voltage input. The switching unit includes a first switch, a second switch and a third switch. The circuit includes a control signal input configured to receive a switch control signal. The circuit includes a signal distribution unit that is configured to output the switch control signal to the first switch delayed by a first time interval and to output the switch control signal to the second switch and to the third switch delayed by a second time interval.

Method and apparatus for providing a voltage to a circuit

In a processor system, different memory means (), which can in each case comprise a memory stack () for the instruction counter, a register () for temporarily storing data and status register (), are provided for various tasks. When an interrupt event (EV) occurs which causes a change from a current task to a new task, a controller () switches from the memory means () allocated to the old task to the memory means () allocated to the new task.

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Riemerling, Germany

Peter Hober