Stmicroelectronics Gmbh

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Stmicroelectronics Design and Application Gmbh

Peter Heinrich

Ernest De Ruiter

Manfred Huber

Stefan Kämper

Kai Mierau

Andreas Arnold

Michael Klemund

Walfred Leinfelder

An integrated circuit, comprises a wakeup terminal; a supply voltage terminal configured to receive a supply voltage; and a power control circuit. The power control circuit comprises an enable circuit coupled to the wakeup terminal and configured to generate a voltage monitoring enable signal as a response to a wakeup signal received at the wakeup terminal, and a voltage monitoring circuit for generating a supply voltage level indication signal. The voltage monitoring circuit is coupled to the supply voltage terminal and comprises an operation switch controlled by the voltage monitoring enable signal. The voltage monitoring circuit is configured to determine if the supply voltage is above a threshold voltage and set the supply voltage level indication signal accordingly. The integrated circuit further comprises processing circuitry, with the supply voltage level indication signal controlling the switching between a normal operation state and a standby state of the processing circuitry.

Integrated circuit operable in a standby mode

The present invention relates to a storage unit for gases, in particular a sorptive storage, with the storage unit comprising a sorbent for the reversible uptake of the gases to be stored and the sorbent being based on discrete sorptive particles. The sorptive particles are embedded in a solid gas-permeable three-dimensional support having a foam structure and/or are fixed thereto. The storage unit is particularly suitable for the storage of combustible or fossil gases, e.g. hydrogen, natural gas and the like, and thus as gas storage unit in power stations and motor vehicles.

Sorptive storage unit for gases

A monitoring circuit for a data transmission network having a plurality of transmissive and receptive network nodes and a double-line bus connecting the network nodes and serving for redundant double transmission of digital communications, with a first line (A) and a second line (B) via which communication pulses transferred in the form of time-spaced pulse sequences are transferred in synchronous manner in terms of time slot, a potential change detector is provided by means of which the two lines can each be monitored for the presence of potential change activities and by means of which a condition can be detected in which, during a pulse sequence, potential change activities occur only on the first line, but not on the second line; and a first time measuring circuit is provided by means of which a time measurement of the duration of such a condition can be carried out, and when a predetermined duration of such a condition is exceeded, an error signal is generated.

Monitoring circuit for a data transmission network

An interface for a data node of a data network including a plurality of data nodes are connected to each other by way of a bus line and activatable in selective manner by address codes transmitted via the bus line. The interface includes an activating address filter allowing addresses intended for the associated data node to be recognized.

Interface for a data node of a data network

Error checking for an electric data transmission system for differential transmission of binary data pulses using two lines, in which the signals on both lines are differentiated each, the resulting differential signals and a reference signal are summed up to form a sum signal, the sum signal is compared with the reference signal on the one hand and the two differential signals are compared with the sum signal on the other hand, and error signals are produced from the result of these comparisons when line errors of a specific kind are present.

Line error checking circuit for an electric data transmission system

A slope control device for an electric data transmission system having a first line and a second line for differentially transmitting binary data pulses in such a manner that a first logic value of the data pulses has a high potential on the first line and a low potential on the second line associated therewith and a second logic value of the data pulses has a low potential on the first line and a high potential on the second line associated therewith, said slope control device being designed such that it regulates the slope steepness of the potential curve of a first one of both lines to a desired value; compares the slope steepness of the potential curve on one line to the slope steepness of the potential curve on the other line; and compares the slope steepness of the potential curve of the second line as a function of the comparison result.

Slope control device for an electric data transmission system

An error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, wherein the system has a number of receiving locations connected via a double-line bus having a first line and a second line. The circuit includes a data output, a decoder having three decoder outputs, of which a first decoder output associated with both lines delivers a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder output associated with the first line delivers a second decoder output signal dependent on the difference between the potential value of the first line and a first mean potential value, and a third decoder output associated with the second line delivers a third decoder output signal dependent on the difference between the potential value of the second line and a second mean potential value. A line condition detector circuit detects error-free line conditions, line errors of the first line, and line errors of the second line, depending on the decoder output signals, and changeover control signals can be delivered to a changeover switch to deliver properly decoded data, depending on the particular detection result.

Error processing circuit for a receiving location of a data transmission system

A method of and a circuit arrangement for data transfer between a master means and slave means, in which bit sequences are transferred each having an address field for addressing the respective slave means to be controlled, a control field for control information, and a data field. The data bit number of the data field may be different depending on the addressed slave means. The bit sequences transmitted from the master means are read back directly to the master means, so that the occurrence of corrupt bits in the bit sequence is recognized and a transfer of the bit sequence recognized as corrupt to the addressed slave means can be prevented.

Method of and circuit arrangement for digitally transferring bit sequences in selective manner

A comparator having a differential amplifier with a signal input to receive an input signal and a reference input to receive a reference voltage, and having a controllable bias current source for supplying to the differential amplifier a bias current that has a low quiescent current or a higher active current as a function of whether the input signal is constant or variable. The controllable bias current source is further configured to adjust the bias current in accordance with the rate of change of the input signal.

Comparator with controllable bias current source

An electric circuit configuration for shaping the slew rate of a pulsed output voltage occurring at an output terminal and for detecting a short circuit at the output terminal, having: a switchover control circuit for controlling the slew rate of the output voltage as a function of a voltage curve occurring across an internal resistor in a first switching state, and for feedback-controlling the slew rate as a function of the output voltage curve in a second switching state, and which is in a substantially dead state in a third switching state; a detector circuit which provides a detection signal when the output voltage differs by at least a predetermined value from the output voltage level occurring before edge onset; and a timer circuit for switching the control circuit from the first to the second switching state a predetermined length of time after edge onset if the detection signal is present at this time, and from the first to the third switching state if the detection signal is not present at this time.

Circuit configuration for shaping slew rate

A process is for preparing O-acetylserine, L-cysteine and sulphurous compounds derived therefrom using feedback-resistant serine acetyl transferases. In comparison with the wild-type enzyme, these serine acetyl transferases have reduced sensitivity to the inhibitor L-cysteine and a protein sequence which, in comparison with the wild-type enzyme, displays at least one mutation or deletion. The process has a mutation which lies in the sequence region of the amino acid in position 97 up to and including the amino acid in position 273 or the deletion lies in the carboxy terminal sequence region as from the amino acid in position 227, position 1 being the starter methionine of FIG. 5 (SEQ ID NO:1) and the mutation from Met to Ile in position 256 being excluded.

Process for preparing O-acetylserine, L-cysteine and L-cysteine-related products

A device for selection of address words, each having n bit locations and serving for addressing m different receiving locations of a digital communications apparatus, comprising a digital acceptance device via which address words can be selected which are acceptable for the particular receiving location in consideration. The acceptance device includes an address word segmenting device through which each address word received by the receiving location is subdivided into s address word segments with b segment bit locations each, wherein b=n/s and n is an integral multiple of s, a decoder having a decoder input accepting the bit pattern of the address word segment of the particular address word being examined for acceptance, and having a decoder output at which, for each of the possible segment bit patterns, a decoder output bit pattern representing only this segment bit pattern is available. The device also includes s filter registers associated with one of the address word segments each, for storing filter register bit patterns, a comparison circuit through which the decoder output bit pattern can be compared with the contents of the associated filter register, the output providing an examination result signal which is either a conformity signal or a non-conformity signal. The device also includes an evaluation circuit, that delivers an acceptance signal only when a conformity signal has been present at the output of the comparison circuit for each address word segment of this address word.

Device for selecting address words by demultiplex decoding

A device for the selection of address words each having n bit locations and serving for addressing m different receiving locations of a digital communication module, in at least one of the receiving locations, including a digital acceptance module through which address words can be selected. The device has an address word segmenting module through which each address word received by the receiving location can be subdivided into s address word segments with b segment bit locations each, wherein b=n/s and n is an integral multiple of s. The device further has z digital segment filters whose inputs can each be fed with an address word segment, with each segment filter having the function of examining one address word segment each with respect to conformity with a predetermined segment bit pattern, and a filter output signal being available at the output of the respective segment filter, which in accordance with the examination result is either a conformity signal or a non-conformity signal. Additionally, the device has an activation module through which those segment filters can be activated during the duration of the respective address word segment to be assessed which carry out an examination with respect to such segment bit patterns which can occur in the address words acceptable for the receiving location in consideration, in the respective address word segment to be assessed. Finally, an evaluation module through which the output signals of the respective segment filters activated for the assessment of an address word can be evaluated with respect to the presence of an address word that is acceptable for the receiving location in consideration.

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Rosenheim, Germany

Peter Heinrich