International Business Machines Corporation

Peter H Tallman

Roger E Hough

Peter H Gum

David Paul Brelsford

Thomas O Curlee, Iii

Margaret Croft Enichen

Paul A Malinowski

Roger W Rogers

Gerald Allen Davison

Pamela H Dewey

Lynn A Czak

Sarah T Hartley

Leslie S Coleman

Daniel D Cerutti

A method is disclosed for processing instructions in higher level virtual machines by a 370-XA mode real machine. The real machine and a low level virtual machine each execute a version of the real machine's system control program. The low level virtual machine issues a privileged (SIE) instruction which is simulated by the real machine indicating that instructions in a higher level virtual machine are to be processed. A shadow state description is created and used by the privileged instruction for describing the higher level virtual machine directly to the real machine. Shadow address translation tables are also created in the case when the higher level virtual machine is a pageable machine so that interpretive execution hardware, invoked by the privileged instruction, can translate through the higher level virtual machine translation tables followed by translation through the shadow translation tables. The privileged instruction will, in certain cases, cause the interpretive execution hardware to intercept and interpret storage key manipulating instructions in order to update the real and higher level virtual machine status bits in RCP bytes in response to bit settings in storage key bytes associated with pages which have been accessed or changed. As a result, address translation can occur from a higher level virtual machine absolute storage to the real machine absolute storage.

Instruction processing in higher level virtual machines by a real machine

The embodiments enable address translations for a virtual machine in the TLB (translation lookaside buffer) of a CPU to be retained from exiting a SIE (start interpretive execution) instruction to the next SIE entry to interpretive execution for the same guest (virtual machine CPU). Conditions are defined which determine when guest TLB entries must be invalidated. These conditions require invalidation of guest TLB entries only within and on entry to interpretive execution. A single invalidation of guest TLB entries on entry to interpretive execution is required for any number of conditions recognized while a CPU is not in interpretive execution state. For a guest in a virtual multi-processor (MP) machine, an interlock is provided to allow the use of guest virtual addresses by host instruction simulation and the need for guest TLB invalidation is broadcast to all other real CPUs in a real MP system so that all guest TLBs on all real CPUs can be invalidated to maintain integrity. No broadcast or interlock is needed for a guest in a virtual uni-processor (UP) machine.

Selective guest system purge control

The invention disclosed and claimed herein provides a method for a virtual machine, which maps to the V=R region of a host machine's address space, to resume program execution successfully when the host operating system terminates and subsequently restarts successfully after the occurrence of a system incident. The system incident brings the computer system down, but with a reasonable chance that the system will be able to bounce. A bounce occurs when the host operating system nucleus is reinitialized or refreshed. The virtual machine will be allowed to survive the system incident as long as its integrity can be maintained, i.e. as long as its status and in-progress work can be preserved. The status and in-progress work of the virtual machine is preserved in a reserved region of host storage in such a way that the time to save and restore virtual machine status is reduced, I/O that might cause further system incidents are avoided and the complexity of restoration of the virtual machine during a system incident is reduced.

Recovery of guest virtual machines after failure of a host real machine

Each embodiment enables a single chained queue to have parallel operations by plural element insertion routines and one deletion routine which may be simultaneously executing asynchronously on plural processors for deleting an element, while inserting one or more anchor-pointed elements. This is done by providing a dequeueing lock which is only examined by a program routine which is to delete an element, but is not examined by any program routine which is to make an insertion of an anchor-pointed element into the queue using a System/370 compare and swap instruction. The embodiments provide efficient processing in a non-pure LIFO queue, which is non-pure because the queue can, at the user's option, be used for either LIFO or non-LIFO dequeueing. No lock is used on the queue when inserting anchor-pointed elements. A special case of non-LIFO processing is FIFO (first-in/first-out) processing, which finds the last element in the queue as the required element.

Parallel queueing method

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Poughkeepsie, NY, United States of America

Peter H Tallman