Xilinx, Inc.

Fairchild Camera and Instrument Corp.

Advanced Micro Devices Corporation

Peter H Alfke

Tony K Ngai

Eunice Y D Hao

Wayson J Lowe

Steven P Young

Austin H Lesea

Jennifer Wong

Trevor J Bauer

Charles R Erickson

Scott O Frake

Himanshu J Verma

Nicolas J Camilleri

Eric G Breeze

Colm P Fewer

Robert O Conn

F Erich Goetting

James M Simkins

Raymond C Pang

Venu M Kondapalli

Schuyler E Shimanek

Alvin Y Ching

Brandon Blodget

Thomas E Fischaber

Christopher D Ebeling

Mark A Alexander

Delon Levi

Scott P McMillan

Jane W Sowards

Noel J Brady

Lionel Edward Barker

Michael K Stauffer

Krishna Rallapali

David MacMillan

Charles H Alford

A direct digital synthesis is provided with added circuitry to reduce jitter in an IC so that a programmable frequency output can be provided near the limits of the IC system clock with minimal jitter. The system derives the quotient Q as a remainder R in an accumulator at the instant of an overflow, divided by a programmable input N. The quotient Q is subjected to conversion logic that can be provided by a fast parallel to serial converter such as, for example a multi-gigabit transceiver (MGT) of an FPGA. As an alternative to an MGT, a series of delay devices such as found in a carry chain can be used if calibration is performed to assure the accuracy of delays.

Direct digital synthesis with reduced jitter

A circuit measures a time interval between a first event and a second event. One or more activity inputs receive a respective signal indicating the first and second events. For each activity input, a respective high-speed serial receiver includes a sampling circuit and a deserializer. The sampling circuit generates sample bits from sampling the respective signal at active edges of a clock signal. The deserializer converts the sample bits into a sequence of parallel data words. The sample bits undergo a first change in response to the first event and a second change in response to the second event. An arithmetic circuit receives the sequence of parallel data words from the respective high-speed serial receiver. The arithmetic circuit determines a number of the sample bits between the first and second changes in the sequence of parallel data words. The number measures the time interval between the first and second events.

Circuit for measuring a time interval using a high-speed serial receiver

Circuits and methods of suppressing signal glitches in an integrated circuit (IC). A glitch on a signal entering a clock buffer, for example, is prevented from propagating through the clock buffer. In some embodiments, a latch is added to an input clock path that detects a transition on the input signal, and then ignores any subsequent transitions for a time delta that is determined by a delay circuit. In some embodiments, a multiplexer circuit is used to select between the input clock signal and the output clock signal, with changes on the input clock signal not being passed through the multiplexer circuit unless the time delta has already elapsed. In some embodiments, the delay is programmable, pin-selectable, or self-adapting.

Glitch-suppressor circuits and methods

A first wire having sidewalls of an integrated circuit is tapered from the proximal end to the distal end to reduce width from the first width to the second width. A second wire, spaced apart from the first wire, the second wire has sidewalls. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. The sidewall capacitor capacitance is progressively reduced responsive to the first wire taper.

Tapered signal lines

An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down ('de-tune') data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.

Reducing noise on a supply voltage in an integrated circuit

Circuit and methods for testing a memory device are disclosed. According to one aspect of the invention, a circuit for testing an asynchronous data transfer comprises a first circuit receiving a stream of data in response to a clock signal in a first clock domain. A second circuit coupled to the first circuit receives the stream of data from the first circuit in response to a low level of an empty signal in the second clock domain. A comparator circuit coupled to receives the stream of data and the output of the second circuit. Specific applications to dual port RAMs as well as implementations in a programmable logic devices are disclosed. Various methods of testing an asynchronous data transfer are also disclosed.

Circuit for and method of testing a memory device

Circuits and methods of concatenating first-in-first-out memory circuits (FIFOs). A concatenated FIFO includes first and second FIFOs. The data output terminals of the first FIFO are coupled to the data input terminals of the second FIFO. The read clock of the second FIFO is the system read clock, and the write clock of the first FIFO is the system write clock. Communication between the first and second FIFOs is controlled by the faster of the two system clocks. A control circuit coupled to both the first and second FIFOs has a local clock input terminal coupled to the read clock input terminal of the first FIFO and the write clock input terminal of the second FIFO. The control circuit is driven by status signals from the first and second FIFOs, and generates a read enable signal for the first FIFO and a write enable signal for the second FIFO.

Circuits and methods of concatenating FIFOs

In an integrated circuit, a layer including a plurality of conductive wires is described. A first wire, having sidewalls, is tapered from a proximal end which has a first width to a distal end which has a second width, to reduce width from the first width to the second width, and the first wire also has a substantially vertical surface. A second wire, spaced apart from the first wire, also has a substantially vertical surface. The first wire and the second wire are each horizontally disposed along side each other forming a part of a sidewall capacitor between facing sidewalls. Capacitors are created between the first substantially vertical surface and the second substantially vertical surface, the capacitors are respectively associated with capacitances and with a plurality of loads, the plurality of loads is progressively reduced responsive to a progressive reduction of the capacitances as associated with the first wire taper.

An FPGA having a programmable frequency output is provided that achieves a (theoretical) M-times reduction in output jitter from a conventional direct digital synthesis (DDS) circuit, by running M accumulator circuits in parallel and combining the outputs in a time-staggered way. I Initially the frequency number N added into the accumulators is varied slightly for each accumulator by multiplying by a number, such as X/16 where X varies from 1 to 16 for each of 16 accumulator circuits. The accumulator circuits are further reconfigured so that the output of a register from a first accumulator provides feedback to the adder input in all of the accumulator circuits. The number of overflowing accumulator registers in a clock cycle will then indicate granularity spatially. To translate spatial granularity to time, a programmable delay circuit is connected to the output of each accumulator register.

Direct digital synthesis with low jitter

A first-in, first-out ('FIFO') memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.

First-in, first-out memory system with reduced cycle latency

A pulse width measurement system is provided with components in an FPGA so that pulse widths can be measured that are smaller than the frequency limits of the FPGA system clock. For the measurement, an incoming pulse is fed into the FPGA to many (e.g. 32) I/O inputs in parallel. Each parallel input is then provided to a programmable delay device with each delay configured to a different ascending delay value. The input transition time is then detected by converting the outputs from the delay devices into data indicating the timing information. In one embodiment the outputs of the delay devices address data stored in BRAMs for later processing in the FPGA to determine the timing information.

Measuring pulse edge delay value relative to a clock using multiple delay devices to address a memory to access the delay value

An integrated circuit having an embedded first-in, first-out ('FIFO') memory system uses an embedded block random access memory ('BRAM'). Counters operate in both the read and write clock domains. A binary adder adds a first selected offset value and to a first pointer address, and the sum is converted to a first gray code value. The first gray code value is compared to a second gray code value that represents a second pointer address. If the first gray code value equals the second gray code value, the output of the comparator is provided to a logic block that produces a status flag (e.g. ALMOST FULL or ALMOST EMPTY) in the correct clock domain.

First-in, first-out buffer system in an integrated circuit

A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.

Large crossbar switch implemented in FPGA

Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.

Growing community of inventors

Los Altos Hills, CA, United States of America

Peter H Alfke