Cisco Technology, Inc.

Adaptec, Inc.

Ikanos Communications, Inc.

Mcdata Corporation

Peter Gunadisastra

Bradley D Erickson

Jason Visneski

Rick Kazuo Yoshida

Joel Richard Goergen

Joseph I Chamdani

Behrooz Rezvani

Ali K Al-Shamma

George Edward Curtis

Mike Sapozhnikov

Dale Smith

Stephen Patrick Kolecki

Jayarama N Shenoy

John Zhongxuan Zhang

Matthew S Rogge

Tsuei-chieh Chiu

Mong Yang

Bradley David Erickson

An apparatus includes a printed circuit board (PCB). The PCB includes a plurality of through-holes extending through the PCB between a PCB first surface and a PCB second surface that opposes the PCB first surface, where each through-hole includes a via extending from the PCB first surface to a depth within the through-hole that is distanced from the PCB second surface. An integrated circuit surface mount is connected at the PCB first surface with vias of the through-holes, and a cable interconnect assembly is surface mount connected at the PCB second surface. The cable interconnect assembly includes a plurality of contact pins, each contact pin extending within a corresponding through-hole and having a sufficient dimension to engage and electrically connect with the via of the corresponding through-hole so as to facilitate exchange of an electrical signal between the integrated circuit and the cable interconnect assembly.

High speed traceless interconnect

A method and apparatus are provided for a secure interconnect between data modules, including a security apparatus within a secured data interconnect apparatus installed with a security chip. The interconnect apparatus may be authenticated prior to enabling a stacking feature. Authentication of a interconnect apparatus may be used to ensure the quality and performance of the interconnect apparatus and the data modules.

Connection device authentication

A method and apparatus are provided for a secure interconnect between data modules, including a security apparatus within a secured data connection device installed with a security chip. The connection device may be authenticated prior to enabling a stacking feature. Authentication of a connection device may be used to ensure the quality and performance of the connection device and the data modules.

Various embodiments provide an apparatus and method for configuring a shared data rate in a stackable interface network. An example embodiment includes detecting a data cable identifier, the data cable identifier being indicative of a first data rate capacity associated with a data cable identified by the data cable identifier; propagating information indicative of the first data rate capacity to at least one of a plurality of network devices connected via stackable network interfaces; receiving information indicative of a second data rate capacity from at least one of the plurality of network devices; determining an appropriate shared data rate from the information indicative of the first data rate capacity and the information indicative of the second data rate capacity; and configuring at least one of the plurality of network devices to communicate via a stackable network interface at the shared data rate.

Multi-speed stack interface

Converting data signals includes determining whether a coupled interface converter paddle coupled to a serdes is a first interface converter paddle or a second interface converter paddle. The first interface converter paddle is associated with a first communication protocol, and the second interface converter paddle is associated with a second communication protocol. The communication protocol associated with the coupled interface converter paddle is identified. Data signals are received from the coupled interface converter paddle, and deserialized according to the identified communication protocol.

Converting data signals in a multiple communication protocol system area network

An apparatus and method is disclosed for minimizing in band distortion in the transmit path of an XDSL modem. The transmit path of an XDSL modem introduces various non-linearities into transmissions in both the frequency and time domains. The current invention provides a means for both determining and correcting for distortion in the time domain. In an embodiment of the invention the apparatus may include a calibrator which may be implemented using the existing analog-to-digital (ADC) conversion and demodulation capabilities on the receive path of the modem or alternately, a dedicated module. During a calibration phase a training signal is injected digitally into the digital-to-analog converter of the transmit path. The analog portion of the transmit path is coupled to a calibrator which measures the corresponding analog response. The correlation between input and response is stored in an analog model. During subsequent training and run-time phases of modem operation an oversampled digital input stream is subject to digital Delta Sigma Modulation (&Dgr;&Sgr;M) with the analog model injected into the feedback path from the quantizer. The injection of the analog model into the feedback improves the noise transfer function (NTF) associated with the &Dgr;&Sgr;M.

Method and apparatus for digital to analog conversion with distortion calibration

An apparatus and method for A/D conversion is provided. The apparatus provides for multi-path multi-channel (MPMC) pipelined A/D conversion. Unlike prior art designs in which the handling of multiple channels requires a linear increase in the associated circuitry and components, the current design scales for multiple channel A/D conversion with less than linear scalability. The A/D converter comprises a plurality of stages and interfaces between adjacent columns of the stages. The stages each include an input, a first output, and a second output. Each of the stages is responsive to an input signal applied to the input to output at the first output a bit signal corresponding to at least one significant bit of the input signal and to output at the second output a residue signal corresponding to a difference between the input signal and the bit signal. The stages are arranged in columns. The interfaces are located between adjacent columns for passing residue signals from an upstream one of the adjacent columns to the inputs of a downstream one of the adjacent columns. At least one interface includes a multiplexer. The multiplexer switchably couples residue signals from at east two of the plurality of stages within the upstream one of the adjacent columns across one of the plurality of stages within the downstream one of the adjacent columns.

A/D multi-channel pipeline architecture

Disclosed is a scan-flop adapted for use in testing integrating of an integrated circuit's core logic and an integrated circuit device incorporating the same. Broadly, the scan-flop comprises a synchronous flip-flop having at least one input adapted to receive selected input data from input terminals of the scan-flop and at least one output operative in response to presence of a clocked enable signal to exhibit a logic state as determined by the selected input data. This output defines a data output terminal for the scan-flop. A logic circuit (e.g., an inverter) is electrically coupled to the flip-flop output and has an output node defining a scan output terminal for the scan-flop, which enables a substantial reduction in capacitive loading due to a scan test. A multiplexer operates in response to a select signal to transmit the selected input data to the flip-flop's input. An integrated circuit device is also disclosed having a plurality of I/O pins defined on a semiconductor die and a logic core disposed therein. The logic core includes at least a first logic chain electrically connected between I/O pins and broadly includes two scan-flops and a logical array electrically interposed therebetween.

Fast-scan-flop and integrated circuit device incorporating the same

A method for controlling clock skew in an integrated circuit which includes a plurality of functional blocks which each contain a control circuit that is in communication with a gated clock includes: a) providing a source clock signal to the control circuit, b) providing a reference clock signal to the control circuit, the reference clock signal being substantially derived from the source clock signal, wherein the reference clock signal has a reference clock phase delay that is greater a phase delay of the gated clock, c) generating a control signal using the reference clock signal and the gated clock, the control signal being arranged to indicate a relationship between the reference clock signal and the gated clock, and d) generating a controlled gated clock using the control signal, wherein the controlled gated clock is generated at least in part by adding a suitable delay to the source clock signal, the controlled gated clock having a controlled gated clock phase delay which is substantially the same as the reference clock phase delay. In some embodiments, the reference clock signal and the source clock signal are provided by a frequency synthesizer.

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Palo Alto, CA, United States of America

Peter Gunadisastra