Infineon Technologies Ag

Qimonda Ag

Other

Infineon Technologies LLC

Qimonda

Peter Gregorius

Paul Wallner

Hermann Ruckerbauer

Johannes Stecker

Michael Bruennert

Martin Streibl

Christoph Bilger

Christian Sichert

Dirk Scheideler

Maurizio Skerlj

Roland Barth

Ralf Schledz

Wolfgang Walthes

Thomas Hein

Thomas Rickes

Georg Braun

Dominique Savignac

George William Alexander

Heinz Mattes

Paul Georg Lindt

Martin Brox

Wolfgang Anton Spirkl

Michael Dieter Richter

Lajos Gazsi

Torsten Hinz

Nicola Da Dalt

Markus Balb

Thilo Schaffroth

Andreas Schneider

Manfred Menke

Bernhard Engl

Martin Maier

Armin Hanneberg

Thomas Duda

Ralf Schedel

Andreas Gärtner

Yukio Fukuzo

Andreas Gaertner

Stefan Dietrich

Daniel Kehrer

Simon Muff

Johannes C Reichart

Peter Laaser

Andre Schaefer

Edoardo Prete

Tim Schoenauer

Otto Schumacher

Andre Schäfer

Martin Renner

Christian Weiss

Abdallah Bacha

Manfred Berroth

Chaitanya Dudha

Markus Groezing

Masthan Devalla

Jörg Bonhaus

Zheng Gu

Petyo Pentchev

Lajos Gaszi

Bernard Engl

Embodiments of the invention provide a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access.

Multi-port DRAM architecture for accessing different memory partitions

A system and method utilize a memory device that may be accessed by a plurality of controllers or processor cores via respective ports of the memory device. Each controller may be coupled to a respective port of the memory device via a data bus. Each port of the memory device may be associated with a predefined section of memory, thereby giving each controller access to a distinct section of memory without interference from other controllers. A common command/address bus may couple the plurality of controllers to the memory device. Each controller may assert an active signal on a memory access control bus to gain access to the command/address bus to initiate a memory access. In some embodiments, a plurality of memory devices may be arranged in a memory package in a stacked die memory configuration.

Method and system including plural memory controllers and a memory access control bus for accessing a memory device

A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.

Interface voltage adjustment based on error detection

A semiconductor memory including a plurality of memory banks disposed on an integrated circuit, each memory bank including an array of memory cells, wherein a first portion of memory cells of the plurality of memory banks has a first access speed and a second portion of memory cells of the plurality of memory banks has a second access speed, wherein the first access speed is different from the second access speed.

Semiconductor memory with memory cell portions having different access speeds

A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.

Memory system with extended memory density capability

Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions.

Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed

The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.

Method and apparatus for determining a skew

Method and device for transmitting outgoing useful signals and an outgoing clock signal. Useful signals and a clock signal are transmitted from a transmitter via a first line pair and a second line pair to a receiver. A first useful signal is transmitted in the form of a modulated difference between the electrical potentials of the first line pair. A second useful signal is transmitted in the form of a modulated difference between the electrical potentials of the second line pair. The clock signal is transmitted in the form of a modulated difference between the average value of the potentials of the first line pair and the average value of the potentials of the second line pair.

Method and device for transmitting outgoing useful signals and an outgoing clock signal

The multi-die memory comprises a first die and a second die. The first die comprises a first group of memory banks, and the second die comprises a second group of memory banks. The first group of memory banks and the second group of memory banks are coupled to a common memory interface. The common memory interface couples the multi-die memory with an internal connection.

Multi-die memory, apparatus and multi-die memory stack

In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved. Each memory chip includes a rank select switching section receiving the separately transferred rank select signal and decoding therefrom signal states which are used to select whether a CAwD signal stream is to be sent to the own memory core and processed or re-driven to the next memory chip and whether a read data stream is to be taken from its own memory core or from a read data input interface to be re-driven to the next memory chip.

Semiconductor memory chip and memory system

A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

Bus termination system and method

In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit being connected to data signal contacts being configured to send data signals, the memory device being configured to send the data signals in a phase and frequency accurate (source synchronous) manner with regard to the read clock signal.

Memory device and memory system comprising a memory device and a memory control device

The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.

Memory circuit

An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.

Integrated circuit with wireless connection

Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.

Method and apparatus for storage device with a logic unit and method for manufacturing same

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Munich, Germany

Peter Gregorius