Qualcomm Incorporated

Peter Graeme Clarke

Sinan Goktepeli

Plamen Vassilev Kolev

George P Imthurn

Qingqing Liang

Sivakumar Kumarasamy

Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.

Non-volatile memory (NVM) structure with front and back gates

A Bipolar Junction Transistor (BJT) comprises an emitter, a collector, and a base between the emitter and the collector. The BJT also comprises an emitter contact on a first side of the BJT, a base contact on the first side of the BJT, and a collector contact on a second side of the BJT. The BJT further comprises a Deep Trench Isolation (DTI) region extending from the first side of the BJT to the second side of the BJT.

Bipolar junction transistor and method of fabricating the same

A resistor may include a semiconductor layer having a source region, a drain region, and a channel region. The channel region may be between the source region and the drain region. The channel region may have a same polarity as the source region and the drain region. The resistor may further include a first inter-metal dielectric (IMD) layer on the channel region. The resistor may further include a front-side gate shield on the first IMD layer. The front-side gate shield may overlap the channel region.

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San Diego, CA, United States of America

Peter Graeme Clarke