Apple Inc.

Peter G Soderquist

Brian Robert Mestan

John D Pape

Joshua P De Cesare

Gerard Richard Williams

Sandeep Kumar Gupta

Bernard Joseph Semeria

Mridul Agarwal

David James Williamson

Pradeep Kanapathipillai

Tyler J Huberty

Eric Jason Furbish

Vivek Venkatraman

Chandan Shantharaj

Stephen G Meier

Yanran Yang

Sahil Kapoor

An apparatus includes a cache memory circuit, a prefetcher circuit, and a prefetch deny list circuit, including a plurality of entries, may be included. The cache memory circuit may be configured to store information retrieved from a lower-level memory. The prefetcher circuit may be configured to generate a prefetch request for a particular prefetch address. The prefetch deny list circuit may be configured to allocate, in response to an indication from the cache memory circuit that a previously prefetched address went unused, a given entry, of the plurality of entries, for the previously prefetched address. The prefetch deny list circuit may be further configured to determine whether a particular address for a particular prefetch request corresponds to an active one of the plurality of entries. In response to a determination that a particular active entry corresponds to the particular address, prefetch deny list circuit may deny the particular prefetch request.

Deny list for a memory prefetcher circuit

Systems, apparatuses, and methods for performing efficient translation lookaside buffer (TLB) invalidation operations for splintered pages are described. When a TLB receives an invalidation request for a specified translation context, and the invalidation request maps to an entry with a relatively large page size, the TLB does not know if there are multiple translation entries stored in the TLB for smaller splintered pages of the relatively large page. The TLB tracks whether or not splintered pages for each translation context have been installed. If a TLB invalidate (TLBI) request is received, and splintered pages have not been installed, no searches are needed for splintered pages. To refresh the sticky bits, whenever a full TLB search is performed, the TLB rescans for splintered pages for other translation contexts. If no splintered pages are found, the sticky bit can be cleared and the number of full TLBI searches is reduced.

Reducing translation lookaside buffer searches for splintered pages

Techniques are disclosed relating to controlling cache replacement. In some embodiments, a computing system performs multiple searches of a data structure, where one or more of the searches traverse multiple links between elements of the data structure. The system may cache, in a traversal cache, traversal information that is usable by searches to skip one or more links traversed by one or more prior searches. The system may store tracking information that indicates a location in the traversal cache at which prior traversal information for a first search is stored. The system may select, based on the tracking information, an entry in the traversal cache for new traversal information generated by the first search. The selection may override a default replacement policy for the traversal cache, e.g., to select the location in the traversal cache to replace the prior traversal information with the new traversal information.

Cache replacement based on traversal tracking

Systems, apparatuses, and methods for limiting translation lookaside buffer (TLB) searches using active page size are described. A TLB stores virtual-to-physical address translations for a plurality of different page sizes. When the TLB receives a command to invalidate a TLB entry corresponding to a specified virtual address, the TLB performs, for the plurality of different pages sizes, multiple different lookups of the indices corresponding to the specified virtual address. In order to reduce the number of lookups that are performed, the TLB relies on a page size presence vector and an age matrix to determine which page sizes to search for and in which order. The page size presence vector indicates which page sizes may be stored for the specified virtual address. The age matrix stores a preferred search order with the most probable page size first and the least probable page size last.

Limiting translation lookaside buffer searches using active page size

Techniques are disclosed relating to controlling cache replacement. In some embodiments, search control circuitry is configured to perform multiple searches of a data structure (e.g., page table walks) where searches traverse multiple links between elements of the data structure. In some embodiments, a traversal cache caches traversal information that is usable by searches to skip one or more links traversed by one or more prior searches. In some embodiments, tracking control circuitry stores tracking information in a first entry, where the tracking information indicates a location in the traversal cache at which prior traversal information for a first search is stored. In some embodiments, replacement control circuitry selects, based on the tracking information in the first entry of the tracking control circuitry, an entry in the traversal cache for new traversal information generated by the first search (which may include selecting the first entry to override a default replacement policy).

Systems, apparatuses, and methods for implementing translation lookaside buffer (TLB) striping to enable efficient invalidation operations are described. TLB sizes are growing in width (more features in a given page table entry) and depth (to cover larger memory footprints). A striping scheme is proposed to enable an efficient and high performance method for performing TLB maintenance operations in the face of this growth. Accordingly, a TLB stores first attribute data in a striped manner across a plurality of arrays. The striped manner allows different entries to be searched simultaneously in response to receiving an invalidation request which identifies a particular attribute of a group to be invalidated. Upon receiving an invalidation request, the TLB generates a plurality of indices with an offset between each index and walks through the plurality of arrays by incrementing each index and simultaneously checking the first attribute data in corresponding entries.

Translation lookaside buffer striping for efficient invalidation operations

Systems, apparatuses, and methods for modifying access permissions in a processor. A processor may include one or more permissions registers for managing access permissions. A first permissions register may be utilized to override access permissions embedded in the page table data. A plurality of bits from the page table data may be utilized as an index into the first permissions register for the current privilege level. An attribute field may be retrieved from the first permissions register to determine the access permissions for a given memory request. A second permissions register may also be utilized to set the upper and lower boundary of a region in physical memory where the kernel is allowed to execute. A lock register may prevent any changes from being made to the second permissions register after the second permissions register has been initially programmed.

Growing community of inventors

Milford, MA, United States of America

Peter G Soderquist