Data General Corporation

Peter G Marshall

Michael L Ziegler

David L Whipple

Ulrich B Goerke

Robert Feldstein

A computing system is disclosed which uses a system busy signal on its system bus to help control access to said bus. One or more requesters can generate a request signal when the system busy signal is not asserted. System busy is asserted along with the request signal(s) and remains asserted until all requesters which generated a request signal have gained access to the bus in order of priority. A freeze signal is generated on the system bus during the address phase of an instruction and a wait signal is generated during each data transfer in the data phase of an instruction. The freeze signal may be generated by a memory control unit, a memory module or a requester.

System for controlling access to computer bus having address phase and

The invention electronically identifies whether a computer module board is placed in the correct mechanical slot in a computer frame. A conductive line is connected to at least one electronic connector location in each mechanical slot in a computer frame. A computer module has open circuit electrical connectors which if put in the correct slot will mate with the locations in the slot in the frame which are connected to the conductive line. The other electrical connections which are used for identification are connected to a ground plane in the computer module board. A voltage source is connected through a resistor to a conductive line in the computer frame producing a high signal. If any computer module board engaged in a slot of the computer frame is in the incorrect slot, a low signal will be caused indicating the fault. The fault signal will be supplied to a power supply controller which prevents operating power from being provided to the computer boards.

Electronic board identification

A memory device is disclosed that operates internally substantially independent of the timing of signals from its associated computer. That is, the timing controls for multiplexing the row and column address into the memory chips as well as the enabling signal for writing information into the chips are controlled by different delay lines so that the memory always operates at its optimal operational speed. In addition, the input and output latches are arranged to receive or output information to or from the computer at a time that is optimal for the computer or other information requester.

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Grafton, MA, United States of America

Peter G Marshall