International Business Machines Corporation

Peter G Ledermann

Luu T Nguyen

Paul Andrew Moskowitz

Timothy C Reiley

Lawrence Shungwei Mok

Thomas Mario Cipolla

Caroline A Kovac

Mark F Bregman

Paul William Coteus

Liam David Comerford

Mark B Ritter

Steve Richard White

Glen Walden Johnson

Rodney T Hodgson

Harry R Bickford

Paul R Hoffman

Linda C Matthew

Stephen Dale Linam

Leonard T Olson

Roger Alan Pollak

David Peter Pagnani

M Lawrence Buller

Ekkehard F Miersch

Terry F Hayden

Peter H Bruhn

Harry J Jones

Christopher A Hicks

Walter V Vilkelis

Barbara J McNelis

Lawrence I Levy

Brian D Arldt

Arthur L Leerssen

Alvin D Nguyen

John Gow, Iii

Uh-Po E Tsou

Ioannis Damianakis

Alvin D Nguyne

Stephen C Steinbach

Stanley K Yu

Raymond E Prime

This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cuboid structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate and within which corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contain solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate surface or the pin-like structures can be adapted for insertion into apertures in a second substrate. The second substrate provides a means for electrically inter-connecting a plurality of these cuboids. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cuboid structures.

Packages for stacked integrated circuit chip cubes

A system for testing chips uses a patterned tape having a patterned array of cantilevered contact leads. The tape serves as an interface between the chip under test and a testing unit by providing conductive leads from the I/O terminals on the chip to an off-chip measuring system. The leads on the array may have balls, tips or other shapes on the end to provide contact with the terminals and compensate for height differences. The tape is a single frame or has a series of arrays each positioned around an opening where the chip will be located when a particular pattern is positioned over that chip for test. The pattern on the tape may be the same array or a different array. The tape is indexed to a new pattern when the old one is damaged or no longer needed. Alignment with the chip is by optical sensing and physical pin movement. The tape may have a flap protruding into an aperture and deflectable to provide for planar contact of the leads to the device under test.

Integrated circuit testing system having a cantilevered contact lead

A method and apparatus to encapsulate a device and joints coupled to conductive leads with an encapsulating material. A fixture has a recess to hold via a vacuum the device in place. Conduits in the fixture supply air around the device to form an air dam that flows outward around the device and the leads. A nozzle supplies a metered amount of material to the surface of the device. By controlling the temperature of the fixture and/or the air forming the air dam, the flow of material can be confined to the surface of the device and the joints as it cures. The method can also provide encapsulant edge capping to reduce device stresses.

Dam for lead encapsulation

A tamper-resistant package for protecting information stored in electronic circuitry is described. An energy source provides energy (electrical current, optical energy, microwave energy or RF energy, for example) within a region occupied by the circuitry to be protected. The energy is applied to an energy distribution system comprising a path or paths for energy distribution. Sensing means are provided which respond to the distribution system for sensing an intrusion. The distribution system includes an arrangement for changing or altering the path or paths over which the energy travels or altering the topology of the path or paths. The sensing means is informed of the appearance of the distribution system and senses an intrusion by comparing the appearance of the path(s) with the predicted appearance. In one embodiment, electrical current is selectively applied to a subset of electrical conductors. The pattern of current flowing in the conductors is sensed and compared to an expected pattern which is determined by the subset of energized conductors. Intrusion is evidenced by a disparity between the pattern of energized paths sensed by the sensing means compared to the pattern predicted by the sensing means. Dynamically varying the identity of the energized paths makes it difficult for an attacker to bypass the tamper detection.

Tamper resistant packaging for information protection in electronic

A nozzle assembly is shown for depositing solder onto a series of conductive surfaces such as the mounting pads of a surface mount integrated circuit board. The nozzle assembly includes a nozzle head which has an interior bore for receiving an elongate heat source. The nozzle head also includes an orifice for receiving solid solder fed within the interior bore to contact the elongate heat source. The interior bore terminates in a solder reservoir for molten solder which is fed within the inteiror bore to contact the elongate heat source. The molten solder is dispensed through a tip opening to deposit uniform amounts of solder on each pad. A source of bleed gas is supplied to the interior of the assembly to protect the component parts and excluse oxygen from the interior of the assembly. A cover gas is also supplied to the solder site to reduce oxidation of the moltent solder and reduce the amount of flux required.

Solder placement nozzle with inert cover gas and inert gas bleed

A nozzle assembly is shown for depositing solder onto a series of conductive surfaces such as the mounting pads of a surface mount integrated circuit board. The nozzle assembly includes an upper nozzle mount and a removeable nozzle head which has an interior bore for receiving a portion of the nozzle mount and an elongate heat source. The nozzle head also includes an orifice for receiving solid solder fed within the interior bore to contact the elongate heat source. The interior bore terminates in a solder reservoir for molten solder which is fed within the interior bore to contact the elongate heat source. The molten solder is dispensed through a tip opening to deposit uniform amounts of solder on each pad.

Solder placement nozzle assembly

Electronic device packaging structures useful for electrically interconnecting an electronic device to a substrate. The structure contains at least two metallization layers with dielectric layers between adjacent to metallization layers. The dielectric layers can have variable thickness. Beam leads can project inwardly in cantilevered fashion over a central aperture through the dielectric layers. The inner ends of the beam leads lie substantially in one plane and can be bonded to contact pads on integrated circuit electronic devices. Beam leads can project outwardly from the metallization layers over outer edges of the dielectric layers for bonding to contact pads on a substrate. Signal leads on metallization layers can be symmetrically arranged between ground and voltage leads to provide optimal impedance properties. These structures are useful for tape automated bonding applications.

Multilevel integrated circuit packaging structures

An integrated circuit chip package is described wherein the chip has an active face including a plurality of input and output pads. The chip is mounted face down on a pluralilty of flexible inner beam leads. The package's outer beam leads are bonded to pads residing on an underlying circuit board. A convective heat sink is thermally mounted to the reverse face of the chip, which heat sink is formed from folded thin metal sheet. The heat sink exhibits both minimum mass, and optimum cooling efficiency. The minimum mass reduces the cost of the heat sink through material savings and minimizes the possibility of damage to the package caused by sudden acceleration. The heat sink, in addition to itself being somewhat flexible, is provided with mounting points which are physically connected to the underlying circuit board via resilient connecting means.

Integrated circuit package with improved cooling means

A tool employing a solder foot to deposit solder on a series of conductive surfaces as the tool moves. In one embodiment, non-wettable blade attached to the tool breaks the film. A pair of sensors coupled to a control circuit monitor the position of the solder foot and the position may be changed as a function of the operation to be performed, i.e. deposit, reflow, standby while tool is moved. In a second embodiment a discrete solder mass is extruded and deposited on a preheated pad. In a third embodiment, solder wire is delivered to an ominidirectional tool for deposition.

Solder deposition system

A tool employing a solder foot to deposit solder on a series of conductive surfaces as the tool moves. In one embodiment, non-wettable blade attached to the tool breaks the film. A pair of sensors coupled to a control circuit monitor the position of the solder foot and the position may be changed as a function of the operation to be performed, i.e. deposit, reflow, standby while tool is moved. In a second embodiment a discrete solder mass is extruded and deposited on a preheated pad. In a third embodiment, solder wire is delivered to an omnidirectional tool for deposition.

An apparatus to encapsulate a device and joints coupled to conductive leads with an encapsulating material. A fixture has a recess to hold via a vacuum the device in place. Conduits in the fixture supply air around the device to form an air dam that flows outward around the device and the leads. A nozzle supplies a metered amount of material to the surface of the device. By controlling the temperature of the fixture and/or the air forming the air dam, the flow of material can be confined to the surface of the device and the joints as it cures. The method can also provide encapsulant edge capping to reduce device stresses.

Automated bonding of chips to tape and formation of bonding structures on Tape Automated Bonding (TAB) packaging structures are provided with bonding balls on the ends of beams leads of the TAB tape. Also balltape bonding balls are aligned on stacked TAB sheets and bonded together to form via interconnections through stacked balltape balls in multilayer, electronic packaging structures. Interconnection structures are provided for a universal chip connection laminate which can be applied between a chip and an MLC package. Area TAB tape, which comprises a modification of TAB tape provides balltape TAB connections by means of balltape bonds to areas within the interior of a chip whose leads are bonded in a TAB tape arrangement to the Inner Lead Bonds of the area tape.

Balltape structure for tape automated bonding, multilayer packaging,

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Pleasantville, NY, United States of America

Peter G Ledermann