Plessey Overseas Limited

Zarlink Semiconductor Limited

Plessey Semiconductors Limited

Broadcom Corporation

Mitel Semiconductor Limited

Peter G Laws

Graham J Fletcher

John Deryk Waters

Viatcheslav Igor Souetinov

An apparatus and method is disclosed to negotiate communications parameters between near field communications (NFC) capable devices. In some embodiments, the NFC capable devices operate in a negotiation phase to negotiate one or more communications parameters prior to transferring information. In other embodiments, the NFC capable devices simultaneously negotiate the one or more communications parameters with the transferring of the information.

Negotiating communication parameters between near field communications (NFC) capable devices

An electrical component structure () comprises a plurality of overlying substantially parallel layers (). Each layer () provides a lattice () comprising a first set of conductive tracks arranged substantially orthogonal to, and electrically connected with, a second set of conductive tracks. Conductive islands () are located in windows of the lattices (), the conductive islands being electrically isolated from the tracks. The lattice () of each layer () is electrically connected to the conductive islands () of the other adjacent layer ().

Electrical component structure

An integrated circuit having a substrate and an LC tank circuit comprises an inductor with parallel capacitors. The capacitors include triple plate integrated capacitors having a highest metal plate, a common middle plate and a lowest metal plate. The lowest plate is connected to a virtual ground node. A control circuit element connected to the middle plate allows the resonant frequency of the tank circuit to be controlled.

Integrated circuit

A frequency doubler circuit arrangement comprises a full wave rectifier circuit having an input and a first terminal, the first terminal being connected to a first supply terminal via a first current source, and the input forming an input of the frequency doubler circuit arrangement. A biased transistor circuit is also provided, having a first terminal connected to the first supply terminal via a second current source and being connected to the first terminal of the rectifier circuit. Output terminals of the rectifier circuit and the biased transistor circuit form differential output terminals of the frequency doubler circuit arrangement. The respective outputs of the rectifier circuit and the biased transistor circuit may be connected to a second supply terminal via either an active filter load or a passive filter load, such as an inductance-capacitance-resistance filter. Such a frequency doubler circuit may be employed in a radiotelephone device such that a single voltage controlled oscillator may be utilized to provide signal sources at more than one operating frequency.

Frequency doubler circuit arrangement

An amplifier circuit arrangement comprises first and second long-tailed pairs of transistors each including an inductor to provide a constant current source for their respective transistor pair. Each of the transistors of the pairs is provided with a bias current on its base electrode. A differential input signal is applied between the base electrode of one transistor, via a dc blocking capacitor and an input terminal, and the base electrode of another transistor, via a dc blocking capacitor and an another input terminal. The collector electrodes of two of the transistors are connected together and to an output terminal. The collector electrodes of the other two transistors similarly are connected together and to the other output terminal. A differential output signal is provided between the output terminals. This connection of the collectors of the transistors, which can be described as parallel connection, provides summation of the differential signals provided by the transistor pairs.

Differential amplifier with two long-tailed pairs of transistors

In a differential amplifier having a pair of emitter follower outputs, power saving is obtained by switching the pull-down currents so that the emitter followers have to provide current to drive the load only in the on direction. The preceding stage is a cascode stage, so that the switching signals for switching the pull-down currents may be derived from the emitter circuits of the cascode stage output transistors.

Integrated circuit amplifier arrangements

A mixer system for a direct conversion receiver, the receiver including an RF input path which is divided into I and Q paths for demodulating from the RF signals I and Q signals in phase quadrature with one another, the mixer system including first and second serially coupled mixer means in the I path, third and fourth serially coupled mixer means in the Q path, and a local oscillator providing a plurality of local oscillator signals in phase quadrature with one another to the mixer means, such that the first mixer means receives a local oscillator signal in phase quadrature to the local oscillator signal applied to the second mixer means, and the third mixer means receives a local oscillator in phase quadrature to that applied to the fourth mixer means.

Mixer for direct conversion receiver

A receiver circuit for data in NRZ1 coding transmitted at high data rates along optical fiber links, wherein in order to overcome problems of phase jitter in the incoming signal, a clock circuit is included comprising a phase locked loop with voltage controlled oscillator for generating a clock signal locked in phase to the incoming data signal, a phase detector for comparing the clock signal with the incoming data signal, a phase frequency detector for comparing the clock signal with a reference clock signal, a multiplexer for switching the phase locked loop to respond either to the output of the phase detector or the phase freqency detector, and a digital counting system for comparing the number of clock pulses generated in a reference period determined by the reference clock, the digital counting system controlling the multiplexer to switch to the output of the phase detector when it is determined that the clock signal is accurately following the reference clock signal.

Broad band VCO control system for clock recovery

A circuit for recovering clock information from an incoming data signal preferably in NRZ1 form, the circuit including a VCO (18) providing a clock signal (CK) to four integrate/hold circuits (I1to I4) which receive an incoming data signal, the integrate/hold circuits providing an error signal to the VCO (18) for adjusting the phase thereof to that of the incoming data signal, the integrate/hold circuits being sequenced by logic (10) to provide within each period of the clock signal three functions: (1) an integration of the incoming data signal in every bit period in which a voltage transition occurs, (2) a holding of the integrated value within a subsequent bit period or periods, and (3) a resetting of the integrated value following the next voltage transition in the incoming data signal, whereby the held integrated value, whose magnitude is dependent of the phase of the clock signal relative to the phase of the incoming data signal, provides said error signal.

Clock driven data sampling circuit

A Manchester code clock and data recovery system comprises an input means which receives an encoded input signal. Data integration and error integration devices are provided which receive modified versions of the input signal and produce signals for presentation to an error modulator. The modulator generates an error signal for controlling a phase lock loop circuit having a voltage controlled oscillator. A first output of the oscillator generates signals for controlling the data integration device over a full bit period, and for controlling the error integration device over a half bit period, in a manner that permits the clock signal to be recovered from the first output of the oscillator, and the data to be recovered from the data integration device which is arranged to generate a Manchester biphase coded signal.

Manchester code clock and data recovery system

A circuit comprising three stages, a differential input stage, a store and integrate stage, and a differential output stage. Both input and output stages are co-operative with enable/disable switching, which switching is controlled by timing signals provided externally to control the periods of integration and data reading. The store and integrate stage comprises a pair of transistors and individual current sources, charge being integrated by a capacitor connected between the transistors. At the end of each period of integration the capacitor may be discharged via these sources, or, parallel sources and a further switch may be added to allow separate reset and hole period provision. Such circuits may be combined and timed out in phased sequence for fastest operation. They may be incorporated in Costas phase-locked loops and used as a means of communication data recovery.

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Wiltshire, United Kingdom

Peter G Laws