Cadence Design Systems, Inc.

Xilinx, Inc.

Peter Frey

Bruce W McGaughy

Jun Kong

Baolin Yang

Kumar Deepak

Pramod Chandraiah

Abhijeet S Kolpekwar

Roger Ng

Alain Darte

Jaideep Muhkerjee

Radharamanan Radhakrishnan

Scott Cranston

Boris Krichevskiy

Disclosed approaches monitor states of a plurality of sets of a plurality of handshake signals. Each set of handshake signals is associated with a respective one sub-circuit of a plurality of sub-circuits. For each sub-circuit, a beginning of an iteration by the sub-circuit is detected based on states of the plurality of handshake signals of the set associated with the sub-circuit. A graphics object is generated in response to detecting the beginning of the iteration. The graphics object is displayed on a display device and overlaid on a timeline associated with the sub-circuit. The graphics object has a bound that corresponds to the beginning of the iteration. The end of the iteration is detected based on the states of the associated set of handshake signals, and the graphics object is bounded on the timeline to indicate the end of the iteration.

Method and system providing visualization of sub-circuit iterations based on handshake signals

System and method for representing analog connectivity in a design written in a hardware description language are disclosed. The method includes detecting a circuit component that does not have explicit connection path in the design, where the circuit component includes one or more lower-level circuit instances arranged in one or more branches in a hierarchical graph. The method further includes creating one or more instances of the circuit component having at least one additional port than the circuit component, creating one or more ports in the corresponding one or more instances of the circuit component for providing at least an explicit connection path, and representing the design using at least the explicit connection path and the one or more ports of the corresponding one or more instances.

Method and system for representing analog connectivity in hardware description language designs

A system for communicating simulation solutions between circuit components in a hierarchical data structure includes a simulator module having one or more computer programs for representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchically arranged set of branches includes a first branch that contains one or more driver leaf circuits and a second branch that also contains one or more receiver leaf circuits, where the first branch and second branch are interconnected in the graph through a third branch at a higher hierarchical level in the graph than the first and second branches. The simulator module further includes computer programs for simulating operation of the one or more driver leaf circuits and the one or more receiver leaf circuits, together, without simulating operation of the third branch to determine a first set of changes in signal conditions shared by the one or more driver leaf circuits and the one or more receiver leaf circuits.

System and method for communicating simulation solutions between circuit components in a hierarchical data structure

System and method for converting a flat netlist into a hierarchical netlist are disclosed. The method includes receiving the flat netlist, traversing the flat netlist in a bottom-up fashion, and identifying isomorphic subcircuits in the flat netlist. The method further includes creating a set of cross-coupling capacitor collections for storing information of cross-coupling capacitors, creating a set of net collections for storing information of isomorphic subcircuits, traversing each hierarchical level of the hierarchical netlist in a top-down fashion, and generating the hierarchical netlist using the set of net collections and the set of cross-coupling capacitor collections.

System and method for converting a flat netlist into a hierarchical netlist

A system for supporting multi-rate simulation of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) partitioning the circuit into a plurality of group circuits, each group circuit includes one or more leaf circuits, where each leaf circuit produces a predictable set of output signals with a given set of input signals, 2) storing the group circuits in a scheduled event queue in accordance with priority in time which the group circuits need to be simulated, 3) retrieving from the scheduled event queue a set of group circuits for simulation within a predetermined time period, 4) distributing the set of group circuits into a set of predefined event lists, where each of the predefined event list stores one or more group circuits of a corresponding event type, and 5) simulating the one or more group circuits in each of the predefined event list in accordance with a rate of change of signal conditions of each individual group circuit. Hence, the system provides an efficient way to support multi-rate simulation by dynamically scheduling and synchronizing multiple group simulation event types and by communicating corresponding isomorphic activities through an efficient port connectivity interface.

System and method for supporting multi-rate simulation of a circuit having hierarchical data structure

A system for adaptive partitioning of circuit components during simulating of a circuit having a hierarchical data structure includes a simulator module having one or more computer programs for 1) selecting a group of leaf circuits from the first branch and the second branch for simulation, where each leaf circuit is represented by a matrix comprising a set of equations, 2) determining a strength of coupling between two or more leaf circuits of the group in accordance with a set of predetermined electrical coupling criteria, 3) if two or more leaf circuits are deemed be strongly coupled, combining the corresponding matrix of each strongly coupled leaf circuit into a combined matrix, and 4) performing computation for the two or more strongly coupled leaf circuits in accordance with the combined matrix. The system adaptively adjusts the group circuit matrix for computing a group of circuits according to the strength of coupling between the circuits. Hence, it achieves higher simulation performance by reducing either the size of the solver matrix when the circuits are loosely connected to each other, or by reducing the number of computational repetitions due to the communication of changes of signal conditions between circuits by combining the individual circuit matrices when such circuits are closely coupled to each other.

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San Jose, CA, United States of America

Peter Frey