International Business Machines Corporation

Peter Feldmann

Soroush Abbaspour

Ying Liu

Barry Jay Rubin

Bhavna Agrawal

Jason David Morsey

Emrah Acar

Steven G Walker

Safar Hatami

Chandramouli Visweswariah

Vladimir P Zolotov

Peter Anton Habitz

Sani Richard Nassif

Tong Li

Joachim Keinert

Debjit Sinha

Howard Harold Smith

Haifeng Qian

Sampath Dechu

Tomasz J Nowicki

Alina Deutsch

Hemlata Gupta

Albert E Ruehli

Grzegorz Michal Swirszcz

Richard Daniel Kimmel

Adil Bhanji

David Wells Winston

Calvin John Bittner

Ayesha Akhter

Revanta Banerji

Ali Sadigh

Ratan Singh

David Ling

Aspects of the present invention provide a solution for calibrating a model of a complex flow system. In an embodiment, a comparison is made between the output from the model and a set of observed values for each of a plurality of nodes in the complex flow system. An adjoint sensitivity is computed for each of the nodes based on the comparison. These computed adjoint sensitivities are used to adjust a set of coefficients of the models. This calibration process can be performed multiple times, periodically and/or continuously to maximize the accuracy of the model.

Automatic calibration of a model for a complex flow system

A method and system to perform clock network analysis of a clock network of an integrated circuit that includes a grid obtains parameters for each transmission line of the clock network that carries a clock signal between a source of the clock signal and the grid. The method also includes obtaining models of nonlinear components of the clock network, and numerically solving a frequency domain nonlinear Harmonic Balance equation to obtain voltage values at an input and an output of each of the nonlinear components. The number of the voltage values obtained is proportional to the number of the nonlinear components. A physical implementation of the integrated circuit is obtained based on the clock network analysis.

Clock network analysis using harmonic balance

A method includes forming a mixed integer linear problem (MILP) capturing at least a plurality of timing windows over which aggressor net(s), electromagnetically coupled to a victim net in a circuit, produce computed cross-talk noise pulses potentially contributing to a maximum noise for the victim net. The MILP is solved to determine the maximum noise at the victim net. Responsive to the maximum noise meeting one or more criteria, at least an indication of the victim net is output. Forming may include forming a linear problem using overlapping timing windows for which noise pulses contribute to the maximum noise and converting the linear problem to the mixed integer linear problem by introducing into the linear problem binary variables that determine whether individual ones of overlapping or non-overlapping noise pulses from the one or more aggressor nets contribute to the maximum noise. Apparatus and program products are also disclosed.

Cross-talk noise computation using mixed integer linear program problems and their solutions

An on-demand table model for semiconductor device evaluation is provided. A method of providing on-demand table models for semiconductor device evaluation, includes measuring one or more measurement values of an instance of a semiconductor device. The method further includes providing, by a processor, a table model of the instance for the semiconductor device evaluation upon receiving a request for the semiconductor device evaluation. The method further includes generating a table entry in the table model for the one or more measurement values, the table entry including one or more evaluation values of an evaluation function for the instance.

On-demand table model for semiconductor device evaluation

A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances.

Method for supporting multiple libraries characterized at different process, voltage and temperature points

A system, method and computer program product for modeling a semiconductor device structure. The system and method implemented includes performing a simulation of the circuit by applying at least one input waveform on a circuit input port, and loading an output port with at least one of output load; determining, at successive time steps of the circuit simulation, a voltage value Vi on the input port, a voltage value Vo on the output port, and a current values (ia) and (ib) on the respective input and output ports. Then there is computed from the respective current value for each successive time step of the simulation, at least one charge value (Qa(Vi, Vo)) and (Qb(Vi, Vo)), respectively, as a function of Vi and Vo voltage values; and generating a nonlinear charge source from the at least one charge value, the nonlinear charge source used in modeling a dynamic behavior of the cell. A voltage controlled charge source (VCCS) is thereby determined by capturing the natural digital circuit cell behavior.

Characterization of nonlinear cell macro model for timing analysis

A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.

Performing reliability analysis of signal wires

A system and method for waveform compression includes preprocessing a collection of waveforms representing cell and/or interconnect response waveforms and constructing a representative waveform basis using linear algebra to create basis waveforms for a larger set of waveforms. The collection waveforms are represented as linear combination coefficients of an adaptive subset of the basis waveforms to compress an amount of stored information needed to reproduce the collection of waveforms. The representation of coefficients may be further compressed by, e.g., analytic representation.

Efficient compression and handling of model library waveforms

In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments.

Moment-based characterization waveform for static timing analysis

A solution for analyzing a circuit using initial charge information is provided. In particular, one or more nodes in a design for the circuit is initialized with an initial charge. The charge can comprise a non-equilibrium charge, thereby simulating the history effect, the impact of a charged particle, electro-static discharge (ESD), and/or the like. Operation of the circuit is then simulated over a set of input cycles based on the initial charge(s). To this extent, the non-equilibrium initial condition solution enables the state of the circuit to be controlled and solves the initial system based on these values. This capability is very useful to condition the circuit at a worst-case, best-case, and/or the like, status. Further, in one embodiment of the invention, a set of equations are provided to implement the non-equilibrium initial charge analysis, which provide a more efficient initialization of the circuit than current solutions.

Charge-based circuit analysis

A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.

Method and system for optimizing a device with current source models

A method and system to improve the performance of an integrated circuit (IC) chip by removing timing violations detected by performing a statistical timing analysis, given distributions of process and environmental sources of variation. The distributions are quantized using a minimum distortion criterion into discrete values. For each timing node of the IC circuit, a discrete minimum and maximum operation is performed on the timing parameters using a subset of combinations of the discrete values. The results of the discrete minimum and maximum operation are then de-quantized and propagated to a subsequent timing node and edge thereof. The process continues until one or more primary inputs and outputs of the IC chip are reached. The design of the IC chip is modified by removing all the timing violations identified.

Order independent method of performing statistical N-way maximum/minimum operation for non-Gaussian and non-linear distributions

An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.

Multiple voltage threshold timing analysis for a digital integrated circuit

An approach for performing arbitrary waveform propagation through a logic gate using timing analysis results is described. In one embodiment, there is an arbitrary waveform propagation tool for determining an effect of noise on a digital integrated circuit having at least one logic gate. A timing analysis component is configured to perform a timing analysis on the at least one logic gate and a noise analysis component is configured to perform a noise analysis. A waveform propagation model synthesizer component is configured to dynamically synthesize a waveform propagation model as a function of the timing analysis. The waveform propagation model synthesizer component is further configured to apply an arbitrary voltage waveform comprising one of a noisy waveform or noise glitch waveform and determine an effect of the arbitrary voltage waveform on the at least one logic gate from the dynamically synthesized waveform propagation model.

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New York, NY, United States of America

Peter Feldmann