Sun Microsystems, Inc.

Oracle America, Inc.

Peter F Lai

Rambabu Pyapali

Aveek Sarkar

Shyam Sundar

Xuejun Yuan

Von-Kyoung Kim

Xiaowei Jin

Raymond A Heald

James M Kaku

Sachin Chopra

Thelma C Taylor

Sriram Satakopan

Aharon Ostrer

Helen Dunn

Yongjun Zhang

Peter L Fu

Yongning Sheng

Yu-Yen Mo

Kong-Fai Woo

Venkat R Podduturi

Shian-Jiun Fu

Jeffrey F Wong

Hsiu-Nien Chen

Ju H Yew

Dakshesh Amin

Xi-An Xu

Xeujun Yuan

Ye Xiong

Xiaochun Gao

Arvindvel Shanmugavel

Shunjiang Xu

Teong Ming Cheah

Samer H Haddad

Vishal Chopra

Kong-Fal Woo

Srirarm Satakopan

An automatic custom block composition tool for composing custom blocks of an integrated circuit (IC) design that may include non-standard library cells. The tool includes program instructions that are executable to create and use a placement control file that includes instructions for use by the custom block composition tool to place the one or more non-standard library cells into the custom block layout. In addition, the program instructions may instantiate a leafcell for each non-standard and each standard library cell included in a netlist. The program instructions may access the placement control file and place each leafcell in a row of the custom block layout according to the placement control file. The program instructions may also pre-route power, clock and critical network signals, and generate a router control file used during remaining routing of the custom block by a conventional router tool.

Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow

The timing response of a circuit path is predicted by modeling the circuit path using two different timing models. The variation between the timing responses produced by each of the timing models is used to generate a correction factor, which is then applied to one of the timing models. Once the correction factor has been applied to a timing model, the model is used to produce a corrected timing prediction for the modeled circuit path.

Method and software for predicting the timing delay of a circuit path using two different timing models

A technique for improving multiple critical timing paths that exhibit similar characteristics has been discovered. The technique efficiently improves multiple critical timing paths by reducing the number of unique critical timing path patterns for analysis. In some embodiments of the present invention a method for use in connection with an integrated circuit design includes identifying distinct timing paths of the integrated circuit design. The distinct timing paths have timing violations. The method includes associating a first plurality of the distinct timing paths with a first set of timing paths. Individual ones of the first plurality belonging to a second set of timing paths and include a first common characteristic. The method includes improving the first set of timing paths based at least in part on an improvement to an individual timing path of the first set of timing paths.

Method to solve similar timing paths

One embodiment of the present invention provides a circuit which blocks a keeper from interfering with a dynamic node during an evaluation phase for a dynamic wide-NOR structure. The circuit contains a precharge device which is coupled to the dynamic node. The precharge device precharges the dynamic node during a precharge phase. The circuit also contains a plurality of parallel pull-down transistors which are coupled to the dynamic node. The pull-down transistors conditionally discharge the dynamic node during the evaluate phase. The keeper sustains a precharged value on the dynamic node, thereby preventing a false evaluation caused by a leakage current through the parallel pull-down transistors. In addition, the circuit contains a feedback gating device which is coupled between the keeper and the dynamic node. During the evaluation phase, the feedback gating device blocks the keeper, so that the parallel pull-down transistors can discharge the dynamic node without interference from the keeper.

Leakage-tolerant dynamic wide-NOR circuit structure

The capacitances of one or more inputs/outputs of a circuit are estimated by using an extraction tool () to extract information associated with the inputs/outputs from a netlist. The information includes information associated with circuit devices directly connected to the inputs/outputs, particularly information related to device connectivity and the feature sizes of the device. Once the information is extracted, a capacitance determination element () aggregates the feature sizes of all the circuit devices connected to each respective input or output, to obtain aggregate feature sizes for each respective input/output. The aggregate feature size is used in determining the total capacitance of the input/output. The total capacitance thus determined can be provided to a timing analysis tool (), which uses the total capacitance of each input or output to generate a timing model for the circuit.

Estimating capacitances using information including feature sizes extracted from a netlist

A technique improves the performance of an integrated circuit design by selectively replacing low Vtransistors with standard Vtransistors. The selection of gates for replacement may be based on a multi-path timing analysis. If a low Vvariant of a gate instance increases a path cycle time as compared to a standard Vcounterpart, the maximum of the path cycle times for all paths that include the low Vvariant and the maximum of the path cycle time for these paths with a standard Vvariant are calculated. If the maximum path cycle time for the path including the low Vvariant is greater than the maximum path cycle time for the path including the standard Vvariant, then that low Vvariant is substituted with a standard Vvariant. Thus, integrated circuit designs prepared in accordance with the invention may exhibit improved cycle times.

Low threshold voltage transistor displacement in a semiconductor device

The present invention describes a method and an apparatus for determining switching power consumption of global devices (e.g., repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time-domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.

Method and apparatus for power consumption analysis in global nets

The present application describes various embodiments of a method and an apparatus for determining electromigration risks for signal nets in integrated circuits. A model for each one of the global nets connecting various circuit blocks in an integrated circuit is created using circuit blocks' timing model and detailed standard parasitic format representation (DSPF) of each global net. The final layout of the integrated circuit is not necessary to determine the electromigration risks. The models can be generated during the early stages of the design cycle once the DSPF of the global nets is available.

Method and apparatus for signal electromigration analysis

The present invention relates to a method and apparatus for a reconfigurable multi-chip module. The reconfigurable multi-chip module includes a processor; a memory module connected to the processor; and a memory control component for controlling whether the processor uses the memory module. The method of producing multi-chip modules includes assembling a processor and a memory module on the multi-chip module; testing the memory module; and selectively configuring the processor to use the memory module based on the testing of the memory module.

Reconfigurable multi-chip modules

The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.

Aggregation of storage elements into stations and placement of same into an integrated circuit or design

Method and system for providing a netlist driven integrated router in a non-netlist driven environment for microprocessor designs includes retrieving top level netlist for the existing microprocessor design from the top level database and the design parameters for the new microprocessor design, and translating these netlist and design parameters at the front end so that the resulting data can be provided to an integrated router which is configured to generate re-routes for the new microprocessor design based on the top level netlist and the design parameters, where the generated re-routes are provided to a back end for translating the re-routes to new top level netlist and merging the new top level netlist with the existing top level netlist database.

Method and system for providing a netlist driven integrated router in a non-netlist driven environment

Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug

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San Jose, CA, United States of America

Peter F Lai