Apple Inc.

Peter F Holland

Mahesh B Chappalli

Brijesh Tripathi

Joseph P Bratt

Christopher P Tann

Brad W Simeral

Hari Ganesh R Thirunageswaram

Timothy John Millet

Arthur L Spence

Ramana V Rachakonda

Shing Horng Choo

Guy Cote

Paolo Sacchetto

Rohit Kumar Gupta

Albert C Kuo

Hao Chen

Assaf Menachem

Gokhan Avkarogullari

Guy Côté

Marc A Schaub

Yingying Tang

Malcolm D Gray

David L Bowman

Chaohao Wang

Hyunwoo Nho

Kingsuk Brahma

Jie Won Ryu

Sheng Zhang

Marc Joseph DeVincentis

Lior Zimet

Koorosh Aflatooni

Benjamin K Dodge

Jenny Hu

Yunhui Hou

Yung-Chin Chen

Graeme M Williams

Ross Thompson

Stephan Lachowsky

Jeffrey J Irwin

Ardra Singh

Shawn P Hurley

Jongyup Lim

Eric Young

Wei Hsin Yao

Manu Gulati

Sukalpa Biswas

Warren S Rieutort-Louis

Joshua P De Cesare

Erik P Machnicki

Marc Albrecht

Weijun Yao

Tong Chen

Robert E Jeter

Shengkui Gao

Gurjeet S Saund

Rakesh L Notani

Mark T Winkler

Hyunsoo Kim

Mohammad Ali Jangda

Vaughn Todd Arnold

Yifan Zhang

Chun Lu

Mark P Rygh

Yuchi Che

Jiayi Jin

Christopher Edward Glazowski

Craig M Okruhlica

Adria Fores Herranz

Tae-Wook Koh

Wenrui Cai

Yue Jack Chu

Can Jin

Maofeng Yang

Alex H Pai

Neeraj Parik

Gihoon Choo

Yongjun Li

Nicolas Pierre Marie Frederic Bonnier

Vincent Z Young

Daniel J Drusch

David A Hartley

Steven T Peltier

Kyounghwan Kim

Kristan Jon Monsen

Zhe Hua

Feng Wen

Hei Kam

Ximeng Guan

Alexandre V Gauthier

Axel B Schumacher

Dinesh M Shedge

Clint M Perlaki

David R Manly

Hyun H Boo

Kevin J Choboter

Pyungwoo Yeon

Lu Yan

Michael Hong Yeol Lim

Na Zhu

To reduce overall power consumption for an electronic display power management integrated circuit (PMIC), one of multiple electric power converters and/or electric power regulators may be selected based on an electrical load (e.g., due to the total brightness of the content displayed) on the electronic display at a given moment. In some embodiments, the PMIC may include a less efficient heavy load converter designed with high-current handling capability and a more efficient light load (e.g., low current) converter with lower current handling capability. A controller may dynamically select between the converters depending on a present load or an expected load on the electronic display.

Content-aware dynamic power converter switching for power optimization

An electronic device may include a display panel. When content of an image frame is expected to consume relatively higher amounts of power, a controller of the electronic device may operate a switch to change a power supply of the display panel to be a power management integrated circuit of the electronic device. However, when content of an image frame is expected to consume relatively less amounts of power, the controller may operate the switch to change the power supply of the display panel to be a power supply of an electronic display, such as a power supply used to power driver circuitry of the electronic display.

Electronic display pipeline power management systems and methods

A light emitter that operates through a display may cause display artifacts, even when the light emitter operates using non-visible wavelengths. Display artifacts caused by a light emitter that operates through a display may be referred to as emitter artifacts. To mitigate emitter artifacts, operating conditions for a display frame may be used to determine an optimal firing time for the light emitter during that display frame. The operating conditions used to determine the optimal firing time may include emitter operating conditions, display content statistics, display brightness, temperature, and refresh rate. Operating conditions from one or more previous frames may be stored in a frame buffer and may be used to help determine the optimal firing time for the light emitter during a display frame. Pixel values for the display may be modified to mitigate emitter artifacts.

Mitigating artifacts caused by an under-display light emitter

In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.

System on a chip that drives display when CPUs are powered down

An electronic device may include processing circuitry configured to generate a first frame of image content and a second frame of image content. The second frame of image content is different from the first frame of image content. The electronic device may also include a display configured to display the first frame of image content at a first refresh rate. In response to receiving the second frame of image content, the electronic device may initially increase the refresh rate before tapering back to the first refresh rate while displaying the second frame of image content.

Frame insertion and frame rate sequencing for panel glitch prevention

Systems, methods, and devices are provided to selectively perform a frame replay at various stages of an image processing pipeline for an electronic display. Image processing circuitry may include first compensation circuitry that compensates for a first compensation factor relating to a first physical parameter of an electronic display and second compensation circuitry that compensates for a second compensation factor relating to a second physical parameter of the electronic display. A first tap point that enables the image frame to be stored and reused may be located between the first compensation circuitry and the second compensation circuitry, while a second tap point may be located after the second compensation circuitry.

Frame replay with selectable taps

Always-on display signal generator

A method may include receiving, via a processor, a frame of image data, such that the frame of image data may include an active portion and an idle portion. The active portion may include data for presenting one or more images via a first display of a first electronic device. The method may also include receiving a signal from a second electronic device during the idle portion of the frame of image data, such that the second electronic device is separate from the first display. The method may then involve initiating processing of the frame of image data in response to the signal being received from the second electronic device.

Follower mode video operation

An electronic display pipeline may process image data for display on an electronic display. The electronic display pipeline may include burn-in compensation statistics collection circuitry and burn-in compensation circuitry. The burn-in compensation statistics collection circuitry may collect image statistics based at least in part on the image data. The statistics may estimate a likely amount of non-uniform aging of the sub-pixels of the electronic display. The burn-in compensation circuitry may apply a gain to sub-pixels of the image data to account for non-uniform aging of corresponding sub-pixels of the electronic display. The applied gain may be based at least in part on the image statistics collected by the burn-in compensation statistics collection circuitry.

Burn-in statistics and burn-in compensation

An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.

Electronic display power management systems and methods

In an embodiment, an integrated circuit includes one or more GPIO pins coupled to a GPIO block in the integrated circuit. At least a first GPIO pin may include corresponding logic circuitry that may be programmed to apply one or more requirements to changes of the digital value received on the first GPIO pin before the change is forwarded to a destination within the integrated circuit. That is, if the requirements are not met for a given change, the logic circuitry may suppress the given change so that it is not provided to other circuits internal to the integrated circuit (e.g. the destination circuit that receives communication via the GPIO pins). The one or more requirements may be a form of hysteresis, for example.

General purpose input/output with hysteresis

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Los Gatos, CA, United States of America

Peter F Holland